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BLOCK DIAGRAM

Input Buffer

DOUT+

DOUT−

DIN+

DIN−

+

Gain Stage

+

+

+

COC2

COC1

DISABLE

LOS

TH

VCC

GND

OUTPOL

Bandgap Voltage

Reference and

Bias Current

Generation

Gain Stage

Gain Stage

Loss of Signal

and

RSSI Detection

Offset

Cancellation

−

RSSI

CML

Output

Buffer

+

−

−

−

−

B0052-01

HIGH SPEED DATA PATH

LOSS OF SIGNAL AND RSSI DETECTION

ONET4201PA

SLLS652 – NOVEMBER 2005

A simplified block diagram of the ONET4201PA is shown in Figure 1.

This compact, low power 4.25 Gbps limiting amplifier consists of a high-speed data path with offset cancellation

block, a loss of signal and RSSI detection block, and a bandgap voltage reference and bias current generation

block.

Figure 1. Simplified Block Diagram of the ONET4201PA

The high-speed data signal is applied to the data path by means of the input signal pins DIN+/DIN–. The data

path consists of the input stage with 2

× 50-Ω on-chip line termination to VCC, three gain stages, which provide

the required typical gain of about 50 dB, and a CML output stage. The amplified data output signal is available at

the output pins DOUT+/DOUT–, which provide 2

× 50-Ω back-termination to VCC. The output stage also includes

a data polarity switching function, which is controlled by the OUTPOL input, and a disable function, controlled by

the signal applied to the DISABLE input pin.

Offset cancellation compensates for internal offset voltages and thus ensures proper operation even for very

small input data signals.

The low frequency cutoff is typically as low as 25 kHz with the built-in filter capacitor.

For applications which require even lower cutoff frequencies, an additional external filter capacitor may be

connected to the COC1/COC2 pins.

The output signal of the input buffer is monitored by the loss of signal and RSSI detection circuitry. In this block a

signal is generated that is linearly proportional to the input amplitude over a wide input voltage range. This signal

is available at the RSSI output pin.

Furthermore, this circuit block compares the input signal to a threshold which can be programmed by means of

an external resistor connected to the TH pin. If the input signal falls below the specified threshold, a loss of signal

is indicated at the LOS pin.

the TH pin can be approximated as given below:

2