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ADSP-21262SKBC-200 Datasheet(PDF) 7 Page - Analog Devices |
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ADSP-21262SKBC-200 Datasheet(HTML) 7 Page - Analog Devices |
7 / 48 page ADSP-21262 Rev. B | Page 7 of 48 | August 2005 •I2S mode • Left-justified sample pair mode Left-justified sample pair mode is a mode where in each frame sync cycle two samples of data are transmitted/received—one sample on the high segment of the frame sync, the other on the low segment of the frame sync. Programs have control over var- ious attributes of this mode. Each of the serial ports supports the left-justified sample pair and I2S protocols (I2S is an industry-standard interface com- monly used by audio codecs, ADCs, and DACs), with two data pins, allowing four left-justified sample pair or I2S channels (using two stereo devices) per serial port, with a maximum of up to 24 audio channels. The serial ports permit little-endian or big-endian transmission formats and word lengths selectable from 3 bits to 32 bits. For the left-justified sample pair and I2S modes, data-word lengths are selectable between 8 bits and 32 bits. Serial ports offer selectable synchronization and transmit modes as well as optional µ-law or A-law companding selection on a per channel basis. Serial port clocks and frame syncs can be internally or externally generated. Serial Peripheral (Compatible) Interface Serial peripheral interface is an industry-standard synchronous serial link, enabling the ADSP-21262 SPI-compatible port to communicate with other SPI-compatible devices. SPI is an Figure 3. ADSP-21262 Memory Map EXTERNAL MEMORY SPACE 0x0020 0000 0x3FFF FFFF ADDRESS RESERVED EXTERNAL DMA ADDRESS SPACE1, 4 0x00FF FFFF 0x0100 0000 0x02FF FFFF 0x0300 0000 RESERVED RESERVED RESERVED RESERVED RESERVED BLOCK 0 ROM (2M BIT) 0x0006 4000–0x0007 7FFF 0x0008 0000 0x0005 8000 0x000B 0000 0x0004 4000–0x0005 7FFF 0x000C 0000 0x0008 8000–0x000A FFFF 0x0000 0000–0x0003 FFFF 0x0004 0000 ADDRESS 0x0011 0000–0x0015 FFFF 0x0016 0000 0x0018 FFFF 0x0019 0000–0x001D FFFF IOP REGISTERS BLOCK 0 SRAM (1M BIT) INTERNAL MEMORY SPACE 0x0010 0000 1EXTERNAL MEMORY IS NOT DIRECTLY ACCESSIBLE BY THE CORE. DMA MUST BE USED TO READ OR WRITE TO THIS MEMORY USING THE SPI OR PARALLEL PORT. 2BLOCK 0 ROM HAS A 48-BIT ADDRESS RANGE (0x000A 0000–0x000A AAAA). 3BLOCK 1 ROM HAS A 48-BIT ADDRESS RANGE (0x000E 0000–0x000E AAAA). 4USE THE EXTERNAL ADDRESSES LISTED HERE WITH THE PARALLEL PORT DMA REGISTERS. THE PARALLEL PORT GENERATES ADDRESS WITHIN THE RANGE 0x0000 0000–0x00FF FFFF. 0x0006 0000 0x0018 0000 0x0010 FFFF 0x000C 7FFF 0x0004 3FFF 0x0006 3FFF LONG WORD ADDRESS SPACE NORMAL WORD ADDRESS SPACE SHORT WORD ADDRESS SPACE 0x0008 7FFF BLOCK 1 SRAM (1M BIT) BLOCK 0 SRAM (1M BIT) BLOCK 0 SRAM (1M BIT) BLOCK 1 SRAM (1M BIT) BLOCK 1 SRAM (1M BIT) RESERVED BLOCK 1 ROM (2M BIT) BLOCK 0 ROM (2M BIT)2 RESERVED BLOCK 1 ROM (2M BIT)3 BLOCK 0 ROM (2M BIT) BLOCK 1 ROM (2M BIT) 0x0007 8000 0x000F 0000 0x0007 FFFF 0x001E 0000 0x0005 FFFF 0x000B FFFF 0x000F FFFF 0x000C 8000–0x000E FFFF 0x0017 FFFF 0x001F FFFF |
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