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IS42S16100C1-7B Datasheet(PDF) 7 Page - Integrated Silicon Solution, Inc

Part # IS42S16100C1-7B
Description  512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS42S16100C1-7B Datasheet(HTML) 7 Page - Integrated Silicon Solution, Inc

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IS42S16100C1
ISSI®
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
7
Rev. D
11/03/06
AC CHARACTERISTICS(1,2,3)
-5
-6
-7
Symbol Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Units
tCK3
Clock Cycle Time
CAS Latency = 3
5
6
7
ns
tCK2
CAS Latency = 2
8
8
8
ns
tAC3
Access Time From CLK(4)
CAS Latency = 3
5
5.5
5.5
ns
tAC2
CAS Latency = 2
6
6
6
ns
tCHI
CLK HIGH Level Width
2
2.5
2.5
ns
tCL
CLK LOW Level Width
2
2.5
2.5
ns
tOH3
Output Data Hold Time
CAS Latency = 3
2
2.0
2.0
ns
tOH2
CAS Latency = 2
2.5
2.5
2.5
ns
tLZ
Output LOW Impedance Time
0
0
0
ns
tHZ3
Output HIGH Impedance Time(5)
CAS Latency = 3
4
5.5
5.5
ns
tHZ2
CAS Latency = 2
6
6
6
ns
tDS
Input Data Setup Time
1.5
1.5
2
ns
tDH
Input Data Hold Time
1
1
1
ns
tAS
Address Setup Time
1.5
1.5
2
ns
tAH
Address Hold Time
1
1
1
ns
tCKS
CKE Setup Time
1.5
1.5
2
ns
tCKH
CKE Hold Time
1
1
1
ns
tCKA
CKE to CLK Recovery Delay Time
1CLK+3 —
1CLK+3
—1CLK+3
—ns
tCS
Command Setup Time (
CS, RAS, CAS, WE, DQM)
1.5
1.5
2
ns
tCH
Command Hold Time (
CS, RAS, CAS, WE, DQM)
1
1
1
ns
tRC
Command Period (REF to REF / ACT to ACT)
48
54
63
ns
tRAS
Command Period (ACT to PRE)
32
36
100,000
42
100,000
ns
tRP
Command Period (PRE to ACT)
16
18
20
ns
tRCD
Active Command To Read / Write Command Delay Time
16
16
16
ns
tRRD
Command Period (ACT [0] to ACT[1])
11
12
14
ns
tDPL3
Input Data To Precharge
CAS Latency = 3
1CLK
1CLK
1CLK
ns
Command Delay time
tDPL2
CAS Latency = 2
1CLK
1CLK
1CLK
ns
tDAL3
Input Data To Active / Refresh
CAS Latency = 3
1CLK+tRP
1CLK+tRP
1CLK+tRP —ns
Command Delay time (During Auto-Precharge)
tDAL2
CAS Latency = 2
1CLK+tRP
1CLK+tRP
1CLK+tRP —ns
tT
Transition Time
1
10
1
10
1
10
ns
tREF
Refresh Cycle Time (4096)
64
64
64
ms
Notes:
1. When power is first applied, memory operation should be started 100 µs after VDD and VDDQ reach their stipulated voltages. Also note that the power-on
sequence must be executed before starting memory operation.
2. Measured with tT = 1 ns.
3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between VIH (min.) and VIL (max.).
4. Access time is measured at 1.4V with the load shown in the figure below.
5. The time tHZ (max.) is defined as the time required for the output voltage to transition by ± 200 mV from VOH (min.) or VOL (max.) when the
output is in the high impedance state.


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