ST7LITE2 datasheet(73/133 Pages) STMICROELECTRONICS

Part #	ST7LITE2

Description	8-BIT MICROCONTROLLER WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI

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ST7LITE2

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SERIAL PERIPHERAL INTERFACE (Cont’d)

11.4.3.3 Master Mode Operation

In master mode, the serial clock is output on the

SCK pin. The clock frequency, polarity and phase

are configured by software (refer to the description

of the SPICSR register).

Note: The idle state of SCK must correspond to

the polarity selected in the SPICSR register (by

pulling up SCK if CPOL=1 or pulling down SCK if

CPOL=0).

How to operate the SPI in master mode

To operate the SPI in master mode, perform the

following steps in order (if the SPICSR register is

not written first, the SPICR register setting (MSTR

bit ) may be not taken into account):

1. Write to the SPICR register:

– Select the clock frequency by configuring the

SPR[2:0] bits.

– Select the clock polarity and clock phase by

configuring the CPOL and CPHA bits. Figure

46 shows the four possible configurations.

Note: The slave must have the same CPOL

and CPHA settings as the master.

2. Write to the SPICSR register:

– Either set the SSM bit and set the SSI bit or

clear the SSM bit and tie the SS pin high for

the complete byte transmit sequence.

3. Write to the SPICR register:

– Set the MSTR and SPE bits

Note: MSTR and SPE bits remain set only if

SS is high.

Important note: if the SPICSR register is not writ-

ten first, the SPICR register setting (MSTR bit)

may be not taken into account.

The transmit sequence begins when software

writes a byte in the SPIDR register.

11.4.3.4 Master Mode Transmit Sequence

When software writes to the SPIDR register, the

data byte is loaded into the 8-bit shift register and

then shifted out serially to the MOSI pin most sig-

nificant bit first.

When data transfer is complete:

– The SPIF bit is set by hardware

– An interrupt request is generated if the SPIE

bit is set and the interrupt mask in the CCR

register is cleared.

Clearing the SPIF bit is performed by the following

software sequence:

1. An access to the SPICSR register while the

SPIF bit is set

2. A read to the SPIDR register.

Note: While the SPIF bit is set, all writes to the

SPIDR register are inhibited until the SPICSR reg-

ister is read.

11.4.3.5 Slave Mode Operation

In slave mode, the serial clock is received on the

SCK pin from the master device.

To operate the SPI in slave mode:

1. Write to the SPICSR register to perform the fol-

lowing actions:

– Select the clock polarity and clock phase by

configuring the CPOL and CPHA bits (see

Figure 46).

Note: The slave must have the same CPOL

and CPHA settings as the master.

– Manage the SS pin as described in Section

11.4.3.2 and Figure 44. If CPHA=1 SS must

be held low continuously. If CPHA=0 SS must

be held low during byte transmission and

pulled up between each byte to let the slave

write in the shift register.

2. Write to the SPICR register to clear the MSTR

bit and set the SPE bit to enable the SPI I/O

functions.

11.4.3.6 Slave Mode Transmit Sequence

When software writes to the SPIDR register, the

data byte is loaded into the 8-bit shift register and

then shifted out serially to the MISO pin most sig-

nificant bit first.

The transmit sequence begins when the slave de-

vice receives the clock signal and the most signifi-

cant bit of the data on its MOSI pin.

When data transfer is complete:

– The SPIF bit is set by hardware

– An interrupt request is generated if SPIE bit is

set and interrupt mask in the CCR register is

cleared.

Clearing the SPIF bit is performed by the following

software sequence:

1. An access to the SPICSR register while the

SPIF bit is set.

2. A write or a read to the SPIDR register.

Notes: While the SPIF bit is set, all writes to the

SPIDR register are inhibited until the SPICSR reg-

ister is read.

The SPIF bit can be cleared during a second

transmission; however, it must be cleared before

the second SPIF bit in order to prevent an Overrun

condition (see Section 11.4.5.2).

1

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