SC4517AEVB datasheet(11/15 Pages) SEMTECH

Part #	SC4517AEVB

Description	1.25MHz, 1.5A Step-Down Switching Regulator

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Manufacturer	SEMTECH [Semtech Corporation]

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11

 2006 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC4517A

Application Information (Cont.)

The loop gain will be given by:

)

s

1

(

)

s

1

(

s

1

s

1

R

C

R

10

125

.

2

)

s

(

G

)

s

(

G

)

s

(

T

2

P

1

P

Z

2

1

2

4

L

3

VD

COMP

ω

+

⋅

ω

+

ω

+

⋅

+

⋅

=

⋅

=

−

Where:

C

R

1

L

1

p

⋅

=

ω

For 1.8V, 2.5V, 3.3V and 5V out applications, their

respective fixed output parts can be used. The FB pins

are connected directly to the outputs. The voltage dividers

(R

1 and R2) have been integrated into the SC4517A

controllers. For other output cases, the adjustable

SC4517A should be used with an external voltage divider.

One integrator is added at origin to increase the DC gain.

ω

Z is used to cancel the power stage pole ωP1 so that the

loop gain has –20dB/dec rate when it reaches 0dB line.

ω

P2 is placed at half switching frequency to reject high

frequency switching noises. Figure 4 gives the asymptotic

diagrams of the power stage with current loop closed

and its loop gain.

ωC

ωP2

ωZ

ωp1

Loop gain T(s)

Power stage

Figure 4. Asymptotic diagrams of power stage with

current loop closed and its loop gain.

The design guidelines for the SC4517A applications are

as following:

1. Set the loop gain crossover corner frequency

ω

C

for given switching corner frequency

ω

C = 2πf

c

.

2. Place an integrator at the origin to increase DC and

low frequency gains.

3. Select

ω

Z such that it is placed at ωP1 to obtain a

-20dB/dec rate to go across the 0dB line.

4. Place a high frequency compensator pole

ω

P2 (ωP2 = πfs) to get the maximum attenuation of

the switching ripple and high frequency noise with

the adequate phase lag at

ω

C.

Layout Guidelines:

In order to achieve optimal electrical and thermal

performance for high frequency converters, special

attention must be paid to the PCB layouts. The goal of

layout optimization is to identify the high di/dt loops and

minimize them. The following guidelines should be used

to ensure proper operation of the converters.

1. A ground plane is suggested to minimize switching

noises and trace losses and maximize heat

transferring.

2. Start the PCB layout by placing the power components

first. Arrange the power circuit to achieve a clean

power flow route. Put all power connections on one

side of the PCB with wide copper filled areas if

possible.

3. The V

IN bypass capacitor should be placed next to

the V

IN and GND pins.

4. The trace connecting the feedback resistors to the

output should be short, direct and far away from any

noise sources such as switching node and switching

components.

5. Minimize the loop including input capacitor, the

SC4517A and freewheeling diode D

2. This loop passes

high di/dt current. Make sure the trace width is wide

enough to reduce copper losses in this loop.

6. Maximize the trace width of the loop connecting the

inductor, freewheeling diode D

2 and the output

capacitor.

7.

Connect the ground of the feedback divider and the

compensation components directly to the GND pin

of the SC4517A by using a separate ground trace.

8. Connect Pin 4 to a large copper area to remove the

IC heat and increase the power capability of the

SC4517A. A few feedthrough holes are required to

connect this large copper area to a ground plane to

further improve the thermal environment of the

SC4517A. The traces attached to other pins should

be as wide as possible for the same purpose.

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