3

HV57009

Symbol

Parameter

Min

Max

Units

Conditions

I

DD

V

-

15

mA

V

I

NN

High voltage supply current

-

-10

µA

Outputs off, HV

(total of all outputs)

I

DDQ

Quiescent V

-

100

µA

All inputs = V

except +IN = V

V

OH

High level output

Data Out

V

-

V

I

HV

OUT

+1.0

V

DD

VI

V

OL

Low level output

Data Out

-

+0.5

V

I

I

IH

High-level logic input current

-

1.0

µA

V

I

IL

Low-level logic input current

-

-1.0

µA

V

I

CS

High output source current

-

-2.0

mA

V

see Figures 1a and 1b

-0.1

-

mA

V

see Figures 1a and 1b

ΔI

CS

HV output source current for I

-

10

%

V

Note:

Current going out of the chip is considered negative

.

Symbol

Parameter

Min

Max

Units

Conditions

f

CLK

Clock frequency

DC

8.0

MHz

Per register

4.5

When cascading devices

t

Clock width high or low

62

-

ns

---

t

SU

Data set-up time before clock rises

20

-

ns

---

t

H

Data hold time after clock rises

15

-

ns

---

t

Time from latch enable to HV

OUT

-

500

ns

C

t

DHL

Delay time clock to data high to low

-

150

ns

C

t

DLH

Delay time clock to data low to high

-

150

ns

C

t

DLE

Delay time clock to LE low to high

45

-

ns

---

t

WLE

LE pulse width

25

-

ns

---

t

SLE

LE set-up time before clock rises

0

-

ns

---

t

Max. allowable clock rise and fall time

(10% and 90% points)

-

100

ns

---