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SC1104XISTRT Datasheet(PDF) 7 Page - Semtech Corporation |
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SC1104XISTRT Datasheet(HTML) 7 Page - Semtech Corporation |
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7 / 14 page  7 © 2006 Semtech Corp. www.semtech.com POWER MANAGEMENT SC1104A/B Theory of Operation (Cont.) When choosing OC trip point one should consider the Tempco of the MOSFETs Rds_on and SC1104’s Vtrip. Also, any ringing on the Vcc and Phase nodes due to parasitic L and C will have some effect on the OC Vtrip. Example: Iout_nom = 6A; assume I_max = 125% • Iout_nom = 7.5A Rds_on = 0.014 Ω; assume Rds_on_max ≈ 150% • Rds_on = 0.02 Ω Voc = 7.5A • 0.02 Ω = 150mV. This proves that MOSFETs with R DS_ON = 0.014Ω @ 25°C is the right choice. Soft Start The soft start (or hiccup) circuitry is activated when a fault occurs. Faults occur for three reasons: 1) Under voltage (V CC < 4.2V) 2) Over temperature (die temperature > 150°C) 3) Over current in high side FET. All faults are handled the same way. Both DH and DL are forced low. The error amplifier is turned off, but a 2µA current flows into the comp pin (soft start current). The sink current reduces the Comp voltage down to 0.6V over a period of a few milliseconds. When Vcomp ~ 0.6V, the fault is cleared and the DL goes high. Also, the soft start current changes polarity and begins to increase the voltage on the Comp capacitor. The DH remains low, be- cause Vcomp is less than the lowest excursion of the oscillator ramp (1.0V). After a few ms, the Vcomp in- creases to about 1.0V and the DH will start to switch. The duty cycle will gradually increase, and Vsns will in- crease. When Vsns ~ 1.00V, the error amplifier turns on again. The circuit has now reached its operating point. If a fault occurs during the soft start, the cycle will begin again (drivers low, Vcomp decreasing down to 0.6V). Closing the Loop In order to have a stable closed loop system with optimum transient response one should make sure that open-loop frequency response has an adequate Gain & Phase margins. The Bode plot of log. Gain vs Freq. and Phase vs Freq. provide the necessary means for the circuit evaluation. Loop stability defined by compensation networks around transconductance error amplifier (EA) and output divider, see below and output capacitor Cout and inductor Lout. Cp Cn Ra Rn Rb + _ Vref Vout EA Gm Typical transconductance error amplifier The inductor and output capacitor form a “double pole” at the frequency: ∏ • • • = Co Lo 2 1 f LC The ESR of the output capacitor and the output capacitor value create a “zero” at the frequency. ∏ • • • = Co ESR 2 1 f ESR The “zero” and “pole” from the EA compensation network are: ∏ • • • = Cc Rc 2 1 f Z ∏ • • • = Cp Rc 2 1 f P The additional “lead” network R A, CN, RN can be used to improve phase margin in case when output capacitors with extra-low ESR are used and there is a need to compensate for “high quality” output Lo, Co filter. C C R C |
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