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SST29SF040-55-4I-NH Datasheet(PDF) 2 Page - Silicon Storage Technology, Inc |
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SST29SF040-55-4I-NH Datasheet(HTML) 2 Page - Silicon Storage Technology, Inc |
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2 / 22 page  2 Data Sheet 4 Mbit Small-Sector Flash SST29SF040 / SST29VF040 ©2004 Silicon Storage Technology, Inc. S71160-10-000 2/04 Read The Read operation of the SST29SF040 and SST29VF040 devices are controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is con- sumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 3). Byte-Program Operation The SST29SF040 and SST29VF040 devices are pro- grammed on a byte-by-byte basis. Before programming, the sector where the byte exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Pro- tection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initi- ated after the rising edge of the fourth WE# or CE#, which- ever occurs first. The Program operation, once initiated, will be completed, within 20 µs. See Figures 4 and 5 for WE# and CE# controlled Program operation timing diagrams and Figure 15 for flowcharts. During the Program opera- tion, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored. Sector-Erase Operation The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The SST29SF040 and SST29VF040 offer Sector-Erase mode. The sector archi- tecture is based on uniform sector size of 128 Bytes. The Sector-Erase operation is initiated by executing a six-byte- command sequence with Sector-Erase command (20H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (20H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase opera- tion can be determined using either Data# Polling or Toggle Bit methods. See Figure 8 for timing waveforms. Any com- mands issued during the Sector-Erase operation are ignored. Chip-Erase Operation The SST29SF040 and SST29VF040 devices provide a Chip-Erase operation, which allows the user to erase the entire memory array to the “1s” state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a six- byte Software Data Protection command sequence with Chip-Erase command (10H) with address 555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 9 for timing diagram, and Figure 18 for the flowchart. Any commands written during the Chip- Erase operation will be ignored. Write Operation Status Detection The SST29SF040 and SST29VF040 devices provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the ris- ing edge of WE# which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asyn- chronous with the system; therefore, either a Data# Poll- ing or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to pre- vent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. |
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