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TAS5508APAGG4 Datasheet(PDF) 78 Page - Texas Instruments

Part No. TAS5508APAGG4
Description  8 Channel Digital Audio PWM Processor
Download  99 Pages
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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TAS5508APAGG4 Datasheet(HTML) 78 Page - Texas Instruments

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Serial Control Interface Register Definitions
72
SLES119 − September 2004
TAS5508A
6.15 Input Mixer Registers (0x41 – 0x48, Channels 1 − 8)
Input mixers 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, and
0x48.
Each gain coefficient is in 28-bit (5.23) format so 0x800000 is a gain of 1. Each gain coefficient is written as
a 32-bit word with the upper 4 bits not used. For 8-gain coefficients, the total is 32 bytes.
Bold indicates the one channel that is passed through the mixer.
Table 6−16. Input Mixer Registers Format (0x41 – 0x48, Channels 1 − 8)
I2C
SUBADDRESS
TOTAL
BYTES
REGISTER
FIELDS
DESCRIPTION OF CONTENTS
DEFAULT STATE
A_to_ipmix[1]
SDIN1−Left (Ch 1) A to Input Mixer 1 coefficient (default = 1)
U (31:28), A_1 (27:24), A_1 (23:16), A_1 (15:8), A_1 (7:0)
0x00, 0x80, 0x00, 0x00
B_to_ipmix[1]
SDIN1−Right (Ch 2) B to Input Mixer 1 coefficient (default = 0)
U (31:28), B_1 (27:24), B_1 (23:16), B_1 (15:8), B_1 (7:0)
0x00, 0x00, 0x00, 0x00
C_to_ipmix[1]
SDIN2−Left (Ch 3) C to Input Mixer 1 coefficient (default = 0)
U (31:28), C_1 (27:24), C_1 (23:16), C_1 (15:8), C_1 (7:0)
0x00, 0x00, 0x00, 0x00
0x41
32
D_to_ipmix[1]
SDIN2−Right (Ch 4) D to Input Mixer 1 coefficient (default = 0)
U (31:28), D_1 (27:24), D_1 (23:16), D_1 (15:8), D_1 (7:0)
0x00, 0x00, 0x00, 0x00
0x41
32
E_to_ipmix[1]
SDIN3−Left (Ch 5) E to Input Mixer 1 coefficient (default = 0)
U (31:28), E_1 (27:24), E_1 (23:16), E_1 (15:8), E_1 (7:0)
0x00, 0x00, 0x00, 0x00
F_to_ipmix[1]
SDIN3−Right (Ch 6) F to Input Mixer 1 coefficient (default = 0)
U (31:28), F_1 (27:24), F_1 (23:16), F_1 (15:8), F_1 (7:0)
0x00, 0x00, 0x00, 0x00
G_to_ipmix[1]
SDIN4−Left (Ch 7) G to Input Mixer 1 coefficient (default = 0)
U (31:28), G_1 (27:24), G_1 (23:16), G_1 (15:8), G_1 (7:0)
0x00, 0x00, 0x00, 0x00
H_to_ipmix[1]
SDIN4−Right (Ch 8) H to Input Mixer 1 coefficient (default = 0)
U (31:28), H_1 (27:24), H_1 (23:16), H_1 (15:8), H_1 (7:0)
0x00, 0x00, 0x00, 0x00
A_to_ipmix[2]
SDIN1−Left (Ch 1) A to Input Mixer 2 coefficient (default = 0)
U (31:28), A_2 (27:24), A_2 (23:16), A_2 (15:8), A_2 (7:0)
0x00, 0x00, 0x00, 0x00
B_to_ipmix[2]
SDIN1−Right (Ch 2) B to Input Mixer 2 coefficient (default = 1)
U (31:28), B_2 (27:24), B_2 (23:16), B_2 (15:8), B_2 (7:0)
0x00, 0x80, 0x00, 0x00
C_to_ipmix[2]
SDIN2−Left (Ch 3) C to Input Mixer 2 coefficient (default = 0)
U (31:28), C_2(27:24), C_2(23:16), C_2(15:8), C_2(7:0)
0x00, 0x00, 0x00, 0x00
0x42
32
D_to_ipmix[2]
SDIN2−Right (Ch 4) D to Input Mixer 2 coefficient (default = 0)
U (31:28), D_2 (27:24), D_2 (23:16), D_2 (15:8), D_2 (7:0)
0x00, 0x00, 0x00, 0x00
0x42
32
E_to_ipmix[2]
SDIN3−Left (Ch 5) E to Input Mixer 2 coefficient (default = 0)
U (31:28), E_2 (27:24), E_2 (23:16), E_2 (15:8), E_2 (7:0)
0x00, 0x00, 0x00, 0x00
F_to_ipmix[2]
SDIN3−Right (Ch 6) F to Input Mixer 2 coefficient (default = 0)
U (31:28), F_2 (27:24), F_2 (23:16), F_2 (15:8), F_2 (7:0)
0x00, 0x00, 0x00, 0x00
G_to_ipmix[2]
SDIN4−Left (Ch 7) G to Input Mixer 2 coefficient (default = 0)
U (31:28), G_2 (27:24), G_2 (23:16), G_2 (15:8), G_2 (7:0)
0x00, 0x00, 0x00, 0x00
H_to_ipmix[2]
SDIN4−Right (Ch 8) H to Input Mixer 2 coefficient (default = 0)
U (31:28), H_2 (27:24), H_2 (23:16), H_2 (15:8), H_2 (7:0)
0x00, 0x00, 0x00, 0x00


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