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TAS5508APAGG4 Datasheet(PDF) 76 Page - Texas Instruments

Part No. TAS5508APAGG4
Description  8 Channel Digital Audio PWM Processor
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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TAS5508APAGG4 Datasheet(HTML) 76 Page - Texas Instruments

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Serial Control Interface Register Definitions
70
SLES119 − September 2004
TAS5508A
6.12 Modulation Index Limit Register (0x16)
Table 6−12. Modulation Index Limit Register
D7
D6
D5
D4
D3
D2
D1
D0
LIMIT
[DCLKS]
MIN WIDTH
[DCLKS]
MODULATION INDEX
0
0
0
1
2
99.2%
0
0
1
2
4
98.4%
0
1
0
3
6
97.7%
0
1
1
4
8
96.9%
1
0
0
5
10
96.1%
1
0
1
6
12
95.3%
1
1
0
7
14
94.5%
1
1
1
8
16
93.8%
6.13 Interchannel Channel Delay Registers (0x1B − 0x22) and Offset Register (0x23)
Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into (0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, and 0x22).
Bits D1 and D0 are Don’t Care.
Table 6−13. Interchannel Channel Delay Registers
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
0
0
0
0
0
Minimum absolute delay, 0 DCLK cycles, default for channel 1
0
1
1
1
1
1
Maximum positive delay, 31 x 4 DCLK cycles
1
0
0
0
0
0
Maximum negative delay, −32 x 4 DCLK cycles
1
0
0
0
0
0
Default value for Channel 1: −32
0
0
0
0
0
0
Default value for Channel 2: 0
1
1
0
0
0
0
Default value for Channel 3: −16
0
1
0
0
0
0
Default value for Channel 4: 16
1
0
1
0
0
0
Default value for Channel 5: −24
0
0
1
0
0
0
Default value for Channel 6: 8
1
1
1
0
0
0
Default value for Channel 7: −8
0
1
1
0
0
0
Default value for Channel 8: 24
The offset register is mapped into 0x23.
Table 6−14. Channel Offset Register
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
0
0
0
0
0
0
0
Minimum absolute offset, 0 DCLK cycles default for channel 1
1
1
1
1
1
1
1
1
Maximum absolute delay, 255 DCLK cycles


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