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TAS5508APAGG4 Datasheet(PDF) 49 Page - Texas Instruments

Part No. TAS5508APAGG4
Description  8 Channel Digital Audio PWM Processor
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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TAS5508APAGG4 Datasheet(HTML) 49 Page - Texas Instruments

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TAS5508A Controls and Status
41
SLES119 − September 2004
TAS5508A
2.3.8 Inter-channel Delay
An 8-bit value can be programmed to each of the eight PWM inter-channel delay registers to add a delay per
channel from 0 to 255 clock cycles. The delays correspond to cycles of the high-speed internal clock, DCLK.
The default values are shown in Table 2−9.
Table 2−9. Inter-Channel Delay Default Values
I2C SUB-ADDRESS
CHANNEL
INTER-CHANNEL DELAY DEFAULT (DCLK PERIODS)
0x1B
1
−24
0x1C
2
0
0x1D
3
−16
0x1E
4
+16
0x1F
5
−24
0x20
6
+8
0x21
7
−8
0x22
8
+24
This delay is generated in the PWM and can be changed at any time through the serial control interface I2C
registers 0x1B – 0x22. The absolute offset for channel 1 is set in I2C sub-address 0x23.
NOTE:If used correctly, setting the PWM channel delay can optimize the performance of a
pure path digital amplifier system. The setting is based upon the type of backend power device
that is used and the layout. These values are set during initialization using the I2C serial
interface. Unless otherwise noted, use the default values given in Table 2−9.
2.4
Master Clock and Serial Data Rate Controls
The TAS5508A function only as a receiver of the MCLK (master clock), SCLK (shift clock), and LRCLK
(left/right clock) signals that controls the flow of data on the four serial data interfaces. The 13.5-MHz external
crystal allows the TAS5508A to automatically detect MCLK and the data rate.
The MCLK frequency can be 64 x Fs, 128 x Fs, 196 x Fs, 256 x Fs, 384 x Fs, 512 x Fs, or 768 x Fs.
The TAS5508A operates with the serial data interface signals LRCLK and SCLK synchronized to MCLK.
However, there is no constraint as to the phase relationship of these signals. The TAS5508A accepts a 64 x
Fs SCLK rate and a 1 x Fs LRCLK.
If the phase of SCLK or LRCLK drifts more than ±10 MCLK cycles since the last RESET, the TAS5508A
performs a clock error and resynchronize the clock timing.
The clock and serial data interface have several control parameters:
MCLK Ratio 64 Fs, 128 Fs, 196 Fs, 256 Fs, 384 Fs, 512 Fs, or 768 Fs) − I2C parameter
Data Rate 32, 38, 44.1,48, 88.2, 96, 176.4, 192 kHz − I2C parameter
AM Mode Enable / Disable − I2C parameter
During AM interference avoidance, the clock control circuitry utilizes three other configuration inputs:
Tuned AM Frequency (for AM interference avoidance) (550 − 1750 kHz) − I2C parameter
Frequency Set Select (1−4) − I2C parameter
Sample Rate − I2C parameter or auto detected


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