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M13S256328A Datasheet(PDF) 3 Page - Elite Semiconductor Memory Technology Inc. |
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M13S256328A Datasheet(HTML) 3 Page - Elite Semiconductor Memory Technology Inc. |
3 / 47 page ESMT M13S256328A Elite Semiconductor Memory Technology Inc. Publication Date : May. 2007 Revision : 1.2 3/47 Pin Description (M13S256328A) Pin Name Function Pin Name Function A0~A11, BA0,BA1 Address inputs - Row address A0~A11 - Column address A0~A7, A9 A8/AP : AUTO Precharge BA0, BA1 : Bank selects (4 Banks) DM0~DM3 DQ Mask enable in write cycle. DQ0~DQ31 Data-in/Data-out CLK, CLK Clock input RAS Row address strobe CKE Clock enable CAS Column address strobe CS Chip select WE Write enable VDDQ Supply Voltage for GDQ VSS Ground VSSQ Ground for DQ VDD Power VREF Reference Voltage for SSTL DQS0~DQS3 (for FBGA) Bi- directional Data Strobe. DQS0 correspond to the data on DQ0~DQ7. DQS1 correspond to the data on DQ8~DQ15. DQS2 correspond to the data on DQ16~DQ23. DQS3 correspond to the data on DQ24~DQ31. NC No connection Absolute Maximum Rating Parameter Symbol Value Unit Voltage on any pin relative to VSS VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD supply relative to VSS VDD, VDDQ -1.0 ~ 3.6 V Voltage on VDDQ supply relative to VSS VDDQ -0.5 ~ 3.6 V Storage temperature TSTG -55 ~ +150 C ° Power dissipation PD TBD W Short circuit current IOS 50 mA Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. |
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