M13S256328A datasheet(1/47 Pages) ESMT

Part #	M13S256328A

Description	2M x 32 Bit x 4 Banks Double Data Rate SDRAM

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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ESMT

M13S256328A

Elite Semiconductor Memory Technology Inc.

Publication Date : May. 2007

Revision : 1.2

1/47

DDR SDRAM

2M x 32 Bit x 4 Banks

Double Data Rate SDRAM

Features

JEDEC Standard

Internal pipelined double-data-rate architecture, two data access per clock cycle

Bi-directional data strobe (DQS)

On-chip DLL

Differential clock inputs (CLK and CLK )

DLL aligns DQ and DQS transition with CLK transition

Quad bank operation

CAS Latency : 2; 2.5; 3

Burst Type : Sequential and Interleave

Burst Length : 2, 4, 8, full page

Full page burst length for sequential burst type only

Start address of the full page burst should be even

All inputs except data & DM are sampled at the rising edge of the system clock(CLK)

Data I/O transitions on both edges of data strobe (DQS)

DQS is edge-aligned with data for reads; center-aligned with data for WRITE

Data mask (DM) for write masking only

VDD = 2.3V ~ 2.7V, VDDQ = 2.3V ~ 2.7V

Auto & Self refresh

64ms refresh period (8K cycle)

SSTL-2 I/O interface

144Ball FBGA package

Operating Frequencies :

PRODUCT NO.

MAX FREQ

VDD

PACKAGE

COMMENTS

M13S256328A -5BG

200MHz

2.5V

144 Ball FBGA

Pb-free

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M13S256328A Datasheet(PDF) 1 Page - Elite Semiconductor Memory Technology Inc.

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