Si4133W

Rev. 1.1

9

IF Phase Noise

100 kHz offset

—

–115

—

dBc/Hz

IF Integrated Phase Error

100 Hz to 1 MHz

—

0.7

—

degrees

rms

RF1 Harmonic Suppression

Second Harmonic

—

–28

–20

dBc

RF2 Harmonic Suppression

—

–23

–20

dBc

IF Harmonic Suppression

—

–26

–20

dBc

RFOUT Output Power Level

–8

–3

0.5

dBm

–5

–1

1

dBm

IFOUT Output Power Level

–7.5

–4

–1

dBm

IF Output Voltage Level

—0.30—

RF1 Output Reference Spurs

Offset = 200 kHz

—

–65

—

dBc

Offset = 400 kHz

—

–70

—

dBc

Offset = 600 kHz

—

–75

—

dBc

RF2 Output Reference Spurs

Offset = 200 kHz

—

–65

—

dBc

Offset = 400 kHz

—

–70

—

dBc

Offset = 600 kHz

—

–75

—

dBc

Power Up Request to Synthesizer Ready

Figure 4, Figure 5

—

200

—

µs

Power Down Request to Synthesizer Off

Figure 4, Figure 5

—

—

100

ns

Table 5. Si4133W RF and IF Synthesizer Characteristics (Continued)

Symbol

Test Condition

Min

Typ

Max

Unit

Notes:

2. Low update frequencies have a maximum value of N for stable operation. See Table 8 on page 18.

3. RF1 tuning range is fixed by inductance of internally bonded wires.

4. RF2 VCO center frequency is fixed by inductance of printed circuit board trace or external inductor. To properly design

and layout the external inductor, see “AN31: Inductor Design for the Si41xx Synthesizer Family”.

on page 16.

6. From power up request (PWDNB

↑ or SENB↑ during a write of 1 to bits PDIB and PDRB in Register 2) to synthesizer

ready (settled to within 0.1 ppm frequency error).

7. From power down request (PWDNB

↓, or SENB↑ during a write of 0 to bits PDIB and PDRB in Register 2) to supply