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NPE405L Datasheet(PDF) 10 Page - Applied Micro Circuits Corporation |
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NPE405L Datasheet(HTML) 10 Page - Applied Micro Circuits Corporation |
10 / 54 page Preliminary PowerNP NPe405L Embedded Processor Data Sheet 8 SDRAM Memory Controller The NPe405L Memory Controller provides a low latency access path to SDRAM memory. The memory controller supports four logical banks. Up to 256MB per bank are supported, for a maximum of 1 GB total. Memory access and refresh timing, address and bank sizes, and memory addressing modes are programmable. Features include: • 11x8 to 13x11 row-column address modes (2- and 4-bank devices supported) • Memory bus operates at same frequency as PLB • 32-bit memory interface support • Programmable address range for each bank of memory - 4GB address space • Industry standard 168-pin DIMMS are supported (some configurations) • 200 MHz NPe405H supports up to 100 MHz memory with PC100 support • 266 MHz NPe405H supports up to 133 MHz memory with PC133 support • 4MB to 256 MB per bank • Programmable timing • Auto refresh • Page Mode Accesses with up to 4 open pages • Power Management (self-refresh) • Error Checking and Correction (ECC) support - Standard single error correct, double error detect coverage - Aligned nibble error detect - Address error logging External Bus Controller (EBC) • Supports four ROM, EPROM, SRAM, Flash, and Slave Peripheral I/O banks supported • Up to 66.66MHz operation • Burst and non-burst devices • 8-, 16-bit byte-addressable data bus width support • Latch data on Ready, Synchronous or Asynchronous • Programmable 2K clock-cycle time-out counter with disable for Ready |
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