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TAS3204PAG Datasheet(PDF) 6 Page - Texas Instruments

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Part # TAS3204PAG
Description  AUDIO DSP WITH ANALOG INTERFACE
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
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2.6 I2C Control Interface
2.7 8051 Microcontroller
2.8 Audio Digital Signal Processor Core
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
Sample rate change on the fly should be handled by customer system controller. The TAS3204
device does not include any internal clock error or click/pop detection/management.
Customer-specific DAP filter coefficients must be uploaded by customer system controller on
changing sample rate.
In slave mode, all incoming serial audio data must be synchronous to an incoming LRCLK_IN of 44.1 kHz
or 48 kHz.
The TAS3204 has an I2C slave-only interface (SDA1 and SCL1) for receiving commands and providing
status to the system controller, and a separate master I2C interface (SDA2 and SCL2) to download
programs and data from external memory such as an EEPROM. See Section 6 for more information. I2C
interface is not 5-V tolerant.
The 8051 microcontroller receives and distributes I2C write data. It retrieves and outputs data as
requested from the I2C bus controller. It performs most processing tasks requiring multi-frame processing
cycles. The microprocessor has its own data RAM for storing intermediate values and queuing I2C
commands, a fixed boot program ROM, and a programmable RAM. The microprocessor's boot program
cannot be altered. The microcontroller has specialized hardware for a master and slave interface
operation, volume updates, and a programmable interval-timer interrupt.
The audio digital signal processor core arithmetic unit is a fixed-point computational engine consisting of
an arithmetic unit and data and coefficient memory blocks. The audio processing structure, which can
include mixers, multiplexers, volume, bass and treble, equalizers, dynamic range compression, or
third-party algorithms, is running in the DAP. The 8051 microcontroller has access to DAP resources such
as coefficient RAM and is able to support the DAP with certain tasks; for example, a volume ramp. The
primary blocks of the audio DSP core are:
• 48-bit data path with 76-bit accumulator
• DSP controller
• Memory interface
• Coefficient RAM (1K×28)
• Data RAM – 24-bit upper memory (1K×24), 48-bit lower memory (768×48)
• Program RAM (3K×55)
The DAP is discussed in detail in the following sections.
6
Functional Description
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