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X25170 Datasheet(PDF) 6 Page - IC MICROSYSTEMS

Part No. X25170
Description  SPI Serial E 2 PROM with Block Lock Protection
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Maker  ICMIC [IC MICROSYSTEMS]
Homepage  http://www.icmic.com
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X25170 Datasheet(HTML) 6 Page - IC MICROSYSTEMS

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X25170
Characteristics subject to change without notice.
6 of 15
Figure 3. Write Enable Latch Sequence
01234567
CS
SI
SCK
High Impedance
SO
For the write operation (byte or page write) to be com-
pleted, CS can only be brought HIGH after bit 0 of data
byte N is clocked in. If it is brought HIGH at any other
time the write operation will not be completed. Refer to
Figures 4 and 5 below for a detailed illustration of the
write sequences and time frames in which CS going
HIGH are valid.
Figure 4. Byte Write Operation Sequence
0123456789
10
CS
SCK
SI
SO
High Impedance
Instruction
16 Bit Address
Data Byte
76543210
15 14 13
3210
20 21 22 23 24 25 26 27 28 29 30 31
To write to the status register, the WRSR instruction is
followed by the data to be written. Data bits 0, 1, 4, 5
and 6 must be “0”. This sequence is shown in Figure 6.
While the write is in progress following a status register
or E2PROM write sequence, the status register may be
read to check the WIP bit. During this time the WIP bit
will be HIGH.
Hold Operation
The HOLD input should be HIGH (at VIH) under normal
operation. If a data transfer is to be interrupted HOLD
can be pulled LOW to suspend the transfer until it can
be resumed. The only restriction is the SCK input must
be LOW when HOLD is first pulled LOW, and SCK
must also be LOW when HOLD is released.
The HOLD input may be tied HIGH either directly to
VCC or tied to VCC through a resistor.


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