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IP2003PBF Datasheet(PDF) 1 Page - International Rectifier

Part # IP2003PBF
Description  Synchronous Buck Multiphase Optimized LGA Power Block Intergrated Power Semiconductors, Drivers&Passives
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Manufacturer  IRF [International Rectifier]
Direct Link  http://www.irf.com
Logo IRF - International Rectifier

IP2003PBF Datasheet(HTML) 1 Page - International Rectifier

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1
iP2003PbF
Features:
• Full function multiphase building block
• Output current 40A continuous with no derating up to
T
PCB = 100°C and TCASE = 100°C
• Operating frequency up to 1.0 MHz
• Efficient dual sided cooling
• Small footprint low profile (11mm x 11mm x 2.2mm) package
• Optimized for very low power losses
• LGA interface
• Ease of design
• Proprietary packaging enables ultra low Rthj-case top
Synchronous Buck
Multiphase Optimized LGA Power Block
Integrated Power Semiconductors, Drivers & Passives
Description
The iP2003PbF is a fully optimized solution for high current synchronous buck multiphase applications.
Board space and design time are greatly reduced because most of the components required for each
phase of a typical discrete-based multiphase circuit are integrated into a single 11mm x 11mm x 2.2mm
power block. The only additional components required for a complete multiphase converter are a PWM IC, the
external inductors, and the input and output capacitors.
iPOWIR technology offers designers an innovative board space saving solution for applications
requiring high power densities. iPOWIR technology eases design for applications where component integration
offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for
layout, heat transfer and component selection.
iP2003PbF Power Block
2/15/06
iP2003PbF Internal Block Diagram
MOSFET
Driver with
dead time
control
V
IN
V
SW
PGND
PRDY
ENABLE
PWM
V
DD
SGND
MOSFET
Driver with
dead time
control
V
IN
V
SW
PGND
PRDY
ENABLE
PWM
V
DD
SGND
PD- 97071
Pin #
Pin Name Pin Function
1
VDD
Supply voltage for the internal circuitry.
2
ENABLE
When set to logic level high, internal circuitry
of the device is enabled. When set to logic
level low, the PRDY pin is forced low, the
Control and Sychronous switches are turned
off, and the supply current is less than 10µA.
3
PWM
TTL-level input signal to MOSFET drivers.
4
PRDY
Power Ready - This pin indicates the status of
ENABLE or VDD. This output will be driven
low when ENABLE is logic low or when VDD
is less than 4.4V (typ.). When ENABLE is
logic high and VDD is greater than 4.4V (typ.),
this output is driven high. This output has a
10mA source and 1mA sink capability.
5, 7
PGND
Power Ground - connection to the ground of
bulk and filter capacitors.
6
VSW
Switching Node - connection to the output
inductor.
8
VIN
Input voltage for the DC-DC converter.
PACKAGE
DESCRIPTION
INTERFACE
CONNECTION
PARTS PER
BAG
PARTS
PER
REEL
T & R
ORIENTATION
iP2003PbF
LGA
10
---
iP2003TRPbF
LGA
---
1000
Fig 12
NOT RECOMMENDED FOR NEW DESIGN
REPLACE WITH iP2003APBF


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