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ST72324BK4 Datasheet(PDF) 67 Page - STMicroelectronics |
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ST72324BK4 Datasheet(HTML) 67 Page - STMicroelectronics |
67 / 188 page ST72324B On-chip peripherals 67/188 . 6:5 CP[1:0] CPU Clock Prescaler These bits select the CPU clock prescaler which is applied in different slow modes. Their action is conditioned by the setting of the SMS bit. These two bits are set and cleared by software: 00: fCPU in Slow mode = fOSC2/2 01: fCPU in Slow mode = fOSC2/4 10: fCPU in Slow mode = fOSC2/8 11: fCPU in Slow mode = fOSC2/16 4SMS Slow Mode Select This bit is set and cleared by software. 0: Normal mode. fCPU =fOSC2. 1: Slow mode. fCPU is given by CP1, CP0. See Section 8.2: Slow mode and Section 10.2: Main clock controller with real-time clock and beeper (MCC/RTC) for more details. 3:2 TB[1:0] Time Base control These bits select the programmable divider time base. They are set and cleared by software (see Table 39). A modification of the time base is taken into account at the end of the current period (previously set) to avoid an unwanted time shift. This allows to use this time base as a real-time clock. 1OIE Oscillator interrupt Enable This bit set and cleared by software. 0: Oscillator interrupt disabled 1: Oscillator interrupt enabled This interrupt can be used to exit from Active Halt mode. When this bit is set, calling the ST7 software HALT instruction enters the Active Halt power saving mode. 0OIF Oscillator interrupt Flag This bit is set by hardware and cleared by software reading the MCCSR register. It indicates when set that the main oscillator has reached the selected elapsed time (TB1:0). 0: Timeout not reached 1: Timeout reached Caution: The BRES and BSET instructions must not be used on the MCCSR register to avoid unintentionally clearing the OIF bit. Table 39. Time base selection Counter prescaler Time base TB1 TB0 fOSC2 =4MHz fOSC2 =8MHz 16000 4ms 2ms 0 0 32000 8ms 4ms 0 1 80000 20ms 10ms 1 0 200000 50ms 25ms 1 1 Table 38. MCCSR register description (continued) Bit Name Function |
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