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ADCMP609BRMZ1 Datasheet(PDF) 10 Page - Analog Devices |
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ADCMP609BRMZ1 Datasheet(HTML) 10 Page - Analog Devices |
10 / 12 page ADCMP609 Rev. 0 | Page 10 of 12 With the pin driven low, hysteresis may become large, but in this device, the effect is not reliable or intended as a latch function. CROSSOVER BIAS POINT Rail-to-rail inputs of this type, in both op amps and comparators, have a dual front-end design. Certain devices are active near the VCC rail and others are active near the VEE rail. At some pre- determined point in the common-mode range, a crossover occurs. At this point, normally VCC/2, the direction of the bias current reverses and there are changes in measured offset voltages and currents. The ADCMP609 slightly elaborates on this scheme. Crossover points can be found at approximately 0.8 V and 1.6 V. MINIMUM INPUT SLEW RATE REQUIREMENT With the rated load capacitance and normal good PC board design practice (as discussed in the Optimizing Performance section), these comparators should be stable at any input slew rate with no hysteresis. Broadband noise from the input stage is observed in place of the violent chattering seen with most other high speed comparators. With additional capacitive loading or poor bypassing, oscillation may be encountered. These oscilla- tions are due to the high gain bandwidth of the comparator in combination with feedback through parasitics in the package and PC board. In many applications, chattering is not harmful. |
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