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MB90F342E Datasheet(PDF) 15 Page - Fujitsu Component Limited. |
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MB90F342E Datasheet(HTML) 15 Page - Fujitsu Component Limited. |
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15 / 84 page  MB90340E Series 15 (Continued) Pin No. Pin name I/O Circuit type*3 Function QFP100*1 LQFP100*2 61 59 P84 F General purpose I/O pin. SCK0 Clock I/O pin for UART0 INT15R External interrupt request input pin 62 60 P85 M General purpose I/O pin. SIN1 Serial data input pin for UART1 63 61 P86 F General purpose I/O pin. SOT1 Serial data output pin for UART1 64 62 P87 F General purpose I/O pin. SCK1 Clock I/O pin for UART1 65 63 VCC ⎯ Power (3.5 V to 5.5 V) input pin 66 64 VSS ⎯ GND pin 67 to 70 65 to 68 P90 to P93 F General purpose I/O pins PPG1, 3, 5, 7 Output pins for PPGs 71 to 74 69 to 72 P94 to P97 F General purpose I/O pins OUT0 to OUT3 Waveform output pins for output compares. This function is enabled when the OCU enables waveform output. 75 73 PA0 F General purpose I/O pin. RX0 RX input pin for CAN0 Interface INT8R External interrupt request input pin 76 74 PA1 F General purpose I/O pin. TX0 TX Output pin for CAN0 77 to 84 75 to 82 P00 to P07 G General purpose I/O pins. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. AD00 to AD07 I/O pins for 8 lower bits of the external address/data bus. This function is enabled when the external bus is enabled. INT8 to INT15 External interrupt request input pins. 85 83 P10 G General purpose I/O pin. The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. AD08 I/O pin for the external address/data bus. This function is enabled when the external bus is enabled. TIN1 Event input pin for the reload timer |
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