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MB90483CPFV Datasheet(PDF) 52 Page - Fujitsu Component Limited. |
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MB90483CPFV Datasheet(HTML) 52 Page - Fujitsu Component Limited. |
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52 / 120 page  MB90480/485 Series 52 (1) 16-bit Free Run Timer The 16-bit free run timer is composed of a 16-bit up-down counter and control status register. The counter value of this timer is used as the base timer for the input capture and output compare. • The counter operation provides a choice of eight clock types. • A counter overflow interrupt can be produced. • A mode setting is available to initialize the counter value whenever the output compare value matches the value in the compare clear register. • Register List Compare clear register (CPCLR) Timer counter data register (TCDT) Timer control status register (TCCS) Initial value 000067H XXXXXXXXB Initial value 000066H XXXXXXXXB Initial value 000063H 00000000B Initial value 000062H 00000000B Initial value 000065H 0--00000B Initial value 000064H 00000000B 15 14 13 12 11 10 9 8 R/W R/W R/W R/W R/W R/W R/W R/W CL14 CL15 CL13 CL12 CL11 CL10 CL09 CL08 76 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W CL06 CL07 CL05 CL04 CL03 CL02 CL01 CL00 15 14 13 12 11 10 9 8 R/W R/W R/W R/W R/W R/W R/W R/W T14 T15 T13 T12 T11 T10 T09 T08 76 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W T06 T07 T05 T04 T03 T02 T01 T00 15 14 13 12 11 10 9 8 R/W R/W R/W R/W R/W R/W R/W R/W ⎯ ECKE ⎯ MSI2 MSI1 MSI0 ICLR ICRE 76 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W IVFE IVF STOP MODE SCLR CLK2 CLK1 CLK0 |
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