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MB90980 Datasheet(PDF) 14 Page - Fujitsu Component Limited. |
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MB90980 Datasheet(HTML) 14 Page - Fujitsu Component Limited. |
14 / 48 page MB90980 Series 14 ■ BLOCK DIAGRAM RAM ROM 8 2 X0, X1, RST X0A, X1A MD2, MD1, MD0 SIN0 SOT0 SCK0 SIN1, SIN2 SOT1, SOT 2 SCK1, SCK2 AVCC AVRH AVSS ADTG AN0 to AN7 2 P76, P77 2 P96, P97 PWC0 PWC1 Clock control Circuit CPU F2MC16LX series core Interrupt controller PPG0, PPG1 PPG2, PPG3 8/16-bit PPG AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1 8/16-bit up/down counter IN0, IN1 OUT0, OUT1, OUT2, OUT3, Input/output timer 16-bit input capture × 2 channels 16-bit output compare × 4 channels 16-bit free-run timer TIN0 TOT0 16-bit reload timer IRQ0 to IRQ7 8 External interrupt UART Extended I/O serial interface × 2 channels A/D converter ( 8/10-bit ) PWC × 2 channels I/O port 4 P24 P27 to 8 P30 P37 to 3 P40 P42 to 8 P60 P67 to 5 P70 P74 to 8 P80 P87 to 4 P90 P93 to 4 PA0 PA3 to Communication prescaler SCL SDA I2C interface 2 2 2 8 2 2 2 2 2 2 4 P40 to P42 ( × 3) : with an open drain setting register I2C pin P77 and P76 are N-ch open drain pin (without P-ch) . Note : In the above diagram, I/O ports share internal function blocks and pins. However, when a set of pins is used with an internal module, it cannot also be used as an I/O port. |
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