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MB90980 Datasheet(PDF) 41 Page - Fujitsu Component Limited.

Part No. MB90980
Description  16-bit Proprietary Microcontroller
Download  48 Pages
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Maker  FUJITSU [Fujitsu Component Limited.]
Homepage  http://edevice.fujitsu.com/fmd/en/index.html
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MB90980 Datasheet(HTML) 41 Page - Fujitsu Component Limited.

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MB90980 Series
41
(9) Trigger Input Timing
(VCC
= 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
* : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
(10) Up-down Counter Timing
(VCC
= 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
* : tCP is internal operating clock cycle time. Refer to “ (1) Clock Timing”.
Parameter
Symbol
Pin name
Condi-
tions
Value
Unit
Remarks
Min
Max
Input pulse width
tTRGH,
tTRGL
ADTG,
IRQ0 to IRQ7
5 tCP*
ns
Normal operation
1
⎯µs
Stop mode
Parameter
Symbol
Pin name
Conditions
Value
Unit
Remarks
Min
Max
AIN input “H” pulse width
tAHL
AIN0, AIN1,
BIN0, BIN1
Load
conditions
80 pF
8 tCP*
ns
AIN input “L” pulse width
tALL
8 tCP*
ns
BIN input “H” pulse width
tBHL
8 tCP*
ns
BIN input “L” pulse width
tBLL
8 tCP*
ns
AIN
↑→BIN↑ rise time
tAUBU
4 tCP*
ns
BIN
↑→AIN↓ fall time
tBUAD
4 tCP*
ns
AIN
↓→BIN↑ rise time
tADBD
4 tCP*
ns
BIN
↓→AIN↑ rise time
tBDAU
4 tCP*
ns
BIN
↑→AIN↑ rise time
tBUAU
4 tCP*
ns
AIN
↑→BIN↓ fall time
tAUBD
4 tCP*
ns
BIN
↓→AIN↑ rise time
tBDAD
4 tCP*
ns
AIN
↓→BIN↑ rise time
tADBU
4 tCP*
ns
ZIN input “H” pulse width
tZHL
ZIN0, ZIN1
4 tCP*
ns
ZIN input “L” pulse width
tZLL
4 tCP*
ns
0.8 VCC
IRQ0 to IRQ7
ADTG
0.8 VCC
0.2 VCC
0.2 VCC
tTRGH
tTRGL


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