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MB90378 Datasheet(PDF) 51 Page - Fujitsu Component Limited.

Part No. MB90378
Description  16-bit Proprietary Microcontroller
Download  65 Pages
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Maker  FUJITSU [Fujitsu Component Limited.]
Homepage  http://edevice.fujitsu.com/fmd/en/index.html
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MB90378 Datasheet(HTML) 51 Page - Fujitsu Component Limited.

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MB90378 Series
51
(7) I2C / Multi-address I2C Timing
(VCC
= 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Notes :
• tCP is the internal operating clock cycle time. Refer to “(1) Clock Timings” rating for tCP.
• m is the setting bit of shift clock oscillation defined in the “ICCR register (CS4, CS3)” and “MCCR register
(CS4, CS3)”. Please refer to the MB90378 series H/W manual for details.
• n is the setting bit of shift clock oscillation defined in the “ICCR register (CS2 to CS0)” and “MCCR register
(CS2 to CS0)”. Please refer to the MB90378 series H/W manual for details.
• tDOSU is shown in the interrupt time is longer than the “L” width of SCL.
• SDA and SCL output value is specified on condition that the rise/fall time is “0 ns”.
*1 : At the stop condition or transferring of next byte.
*2 : After setting register bit IBCRH : SCC at restart.
Parameter
Symbol Pin name
Value
Unit
Remarks
Min
Max
Start condition output
tSTA
SCL,
SDA
tCP (m x n/2
− 1) − 20 tCP (m x n/2 − 1) + 20
ns
Master
mode
Stop condition output
tSTO
SCL,
SDA
tCP (m x n/2
+ 3) - 20 tCP (m x n/2 + 3) + 20
ns
Master
mode
Start condition detect
tSTA
SCL,
SDA
tCP
+ 40
ns
Stop condition detect
tSTO
SCL,
SDA
tCP
+ 40
ns
Restart condition output
tSTASU
SCL,
SDA
tCP (m x n/2
+ 3) − 20 tCP (m x n/2 + 3) + 20
ns
Master
mode
Restart condition detect
tSTASU
SCL,
SDA
tCP
+ 40
ns
SCL output “L” width
tLOW
SCL
tCP x m x n/2
− 20
tCP x m x n/2
+ 20
ns
Master
mode
SCL output “H” width
tHIGH
SCL
tCP (m x n/2
+ 2) − 20 tCP (m x n/2 + 2) + 20
ns
Master
mode
SDA output delay
tDO
SDA
tCP x 3
− 20
tCP x 3
+ 20
ns
SDA output setup time
after interrupt
tDOSU
SDA
tCP x m x n/2
− 20
ns
*1
tCP x 4
− 20
ns
*2
SCL input “L” pulse
tLOW
SCL
tCP x 3
+ 40
ns
SCL input “H” pulse
tHIGH
SCL
tCP
+ 40
ns
SDA output setup time
tSU
SDA
40
ns
SDA hold time
tHO
SDA
0
ns


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