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MB90480 Datasheet(PDF) 32 Page - Fujitsu Component Limited.

Part No. MB90480
Description  16-bit Proprietary Microcontroller
Download  120 Pages
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Maker  FUJITSU [Fujitsu Component Limited.]
Homepage  http://edevice.fujitsu.com/fmd/en/index.html
Logo FUJITSU - Fujitsu Component Limited.

MB90480 Datasheet(HTML) 32 Page - Fujitsu Component Limited.

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MB90480/485 Series
32
(Continued)
× : Interrupt request flag is not cleared by the interrupt clear signal.
: Interrupt request flag is cleared by the interrupt clear signal.
: Interrupt request flag is cleared by the interrupt clear signal (stop request present) .
*1 : The Flash write/erase, timebase timer, and watch timer cannot be used at the same time.
*2 : When the 16-bit reload timer underflow interrupt is changed from enable (TMCSR : INTE
= 1) to disable
(TMCSR : INTE
= 0) , disable the interrupt in the interrupt control register (ICR12 : IL2 to 0 : 111B) , then set
the INTE bit to 0.
Note : If there are two interrupt sources for the same interrupt number, the resource will clear both interrupt request
flags at the EI2OS/
µDMAC interrupt clear signal. Therefore if either of the two sources uses the EI2OS/
µDMAC function, the other interrupt function cannot be used. The interrupt request enable bit for the corre-
sponding resource should be set to “0” and interrupt requests from that resource should be handled by
software polling.
Interrupt source
Clear of
EI2OS
µDMAC
channel
number
Interrupt vector
Interrupt control register
Number
Address
Number
Address
I2C interface
(MB90485 series only)
×
×
#39
FFFF60H
ICR14
0000BEH
A/D conversion
15
#40
FFFF5CH
Flash write/erase,
timebase timer, watch timer *1
×
×
#41
FFFF58H
ICR15
0000BFH
Delay interrupt generator
module
×
×
#42
FFFF54H


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