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MB90480 Datasheet(PDF) 80 Page - Fujitsu Component Limited. |
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MB90480 Datasheet(HTML) 80 Page - Fujitsu Component Limited. |
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80 / 120 page 
MB90480/485 Series 80 22. µDMAC The µDMAC is a simplified DMA module with functions equivalent to EI2OS. The µDMAC has 16 DMA data transfer channels, and provides the following functions. • Automatic data transfer between peripheral resources (I/O) and memory. • CPU program execution stops during DMA operation. • Incremental addressing for transfer source and destination can be turned on/off. • DMA transfer control from the µDMAC enable register, µDMAC stop status register, µDMAC status register, and descriptor. • Stop requests from resources can stop DMA transfer. • When DMA transfer is completed, the µDMAC status register sets a flag in the bit for the corresponding channel on which transfer was completed, and outputs a completion interrupt to the interrupt controller. (1) Register List µDMAC enable register Initial value DERH : 0000ADH 00000000B µDMAC enable register Initial value DERL : 0000ACH 00000000B µDMAC stop status register Initial value DSSR : 0000A4H 00000000B µDMAC status register Initial value DSRH : 00009DH 00000000B µDMAC status register Initial value DSRL : 00009CH 00000000B R/W R/W 15 14 13 12 11 10 9 8 EN14 EN15 EN13 EN12 EN11 EN10 EN9 EN8 R/W R/W R/W R/W R/W R/W R/W R/W 76 5 4 3 2 1 0 EN6 EN7 EN5 EN4 EN3 EN2 EN1 EN0 R/W R/W R/W R/W R/W R/W R/W R/W 76 5 4 3 2 1 0 STP6 STP7 STP5 STP4 STP3 STP2 STP1 STP0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 DE14 DE15 DE13 DE12 DE11 DE10 DE9 DE8 R/W R/W R/W R/W R/W R/W R/W R/W 76 5 4 3 2 1 0 DE6 DE7 DE5 DE4 DE3 DE2 DE1 DE0 R/W R/W R/W R/W R/W R/W |
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