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MB90480 Datasheet(PDF) 41 Page - Fujitsu Component Limited.

Part No. MB90480
Description  16-bit Proprietary Microcontroller
Download  120 Pages
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Maker  FUJITSU [Fujitsu Component Limited.]
Homepage  http://edevice.fujitsu.com/fmd/en/index.html
Logo FUJITSU - Fujitsu Component Limited.

MB90480 Datasheet(HTML) 41 Page - Fujitsu Component Limited.

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MB90480/485 Series
41
4.
8/10-bit A/D Converter
The A/D converter converts analog input voltage to digital values, and provides the following features.
• Conversion time : minimum 3.68
µs per channel
(92 machine cycles at 25 MHz machine clock, including sampling time)
• Sampling time : minimum 1.92
µs per channel
(48 machine cycles at 25 MHz machine clock)
• RC sequential comparison conversion method, with sample & hold circuit.
• 8-bit or 10-bit resolution
• Analog input selection of 8 channels
Single conversion mode : Conversion from one selected channel.
Scan conversion mode : Conversion from multiple consecutive channels, programmable selection of up to
8 channels.
Continuous conversion mode : Repeated conversion of specified channels.
Stop conversion mode : Conversion from one channel followed by a pause until the next activation allows to
synchronize with conversion start.
• At the end of A/D conversion, an A/D conversion completed interrupt request can be generated to the CPU.
The interrupt can be used activate the
µDMAC in order to transfer the results of A/D conversion to memory
for efficient continuous processing.
• The starting factor conversion may be selected from software, external trigger (falling edge) , or timer (rising
edge) .
(1) Register List
ADCS2, ADCS1 (Control status register)
ADCR2, ADCR1 (Data register)
ADCS1
Address : 000046H
←Initial value
←Bit attributes
ADCS2
Address : 000047H
←Initial value
←Bit attributes
ADCR1
Address : 000048H
←Initial value
←Bit attributes
ADCR2
Address : 000049H
←Initial value
←Bit attributes
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
76
5
4
3
2
1
0
MD0
0
R/W
MD1
ANS2
ANS1
ANS0
ANE2
ANE1
ANE0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
W
0
R/W
15
14
13
12
11
10
9
8
INT
0
R/W
BUSY
INTE
PAUS
STS1
STS0
STRT
Reserved
X
R
X
R
X
R
X
R
X
R
X
R
X
R
76
5
4
3
2
1
0
D6
X
R
D7
D5
D4
D3
D2
D1
D0
0
W
0
W
0
W
0
W
X
R
X
R
X
R
15
14
13
12
11
10
9
8
ST1
0
W
S10
ST0
CT1
CT0
D9
D8


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