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MB90580C Datasheet(PDF) 42 Page - Fujitsu Component Limited. |
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MB90580C Datasheet(HTML) 42 Page - Fujitsu Component Limited. |
42 / 110 page MB90580C Series 42 2. Timebase Timer The time-base timer consists of a 18-bit timer and an interval interrupt control circuit. Note that the time-base timer uses the oscillation clock regardless of the setting of the MCS bit in the CKSCR. (1) Register configuration (2) Block Diagram • Timebase timer control register bit 15 1413121110 9 8 Address : 0000A9H Reserved TBIE TBOF TBR TBC1 TBC0 TBTC Access (R/W) ( ) ( ) (R/W) (R/W) (W) (R/W) (R/W) Initial value (1) ( ) ( ) (0) (0) (1) (0) (0) TBTC PONR STBR WRST ERST SRST TBC0 TBR TBIE TBOF TBC1 WT1 WT0 WTE WTC WDCS SCE WTC2 WTC1 WTC0 WTR WTIE WTOF WDTC WDTC AND CLR OF CLR 212 214 216 219 TBTRES 29 210 211 212 213 214 215 WTRES 211 213 215 218 210 213 214 215 QR S AND Q R S AND Q R S Main clock Clock input Time-base timer Watchdog reset generator Clock timer Clock input To WDGRST internal reset generator From power-on reset generator Subclock From RST bit in STBYC register From RST pin From hardware standby control circuit Time-base interrupt Clock interrupt Selector Selector Selector 2-bit counter |
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Similar Description - MB90580C |
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