CS201 Series

8

■ DESIGN METHODS

Fujitsu’s Reference Design Flow provides the following functions that help reduce the development time of large

scale, high quality LSIs.

• Statistical Static Timing Analysis (SSTA) improves timing convergence.

• Physical Prototyping enables more accurate estimation of highly reliable designs.

• Layout synthesis with optimized timing is realized by Physical Synthesis Tool.

• High accuracy design environment considers drop in power supply voltage, signal noise, delay penalty and

crosstalk.

• I/O design environment (power line design, assignment and selection of I/Os, package selection) considers

noise.

■ PACKAGES

The CS201 series can use the same packages that were available for the previous series, allowing a smooth

transition from previously developed models.

For details of delivery time, contact Fujitsu.

• FBGA packages

• PBGA packages

• TEBGA packages

• FC-BGA packages