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MB81ES123245-10 Datasheet(PDF) 20 Page - Fujitsu Component Limited. |
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MB81ES123245-10 Datasheet(HTML) 20 Page - Fujitsu Component Limited. |
20 / 42 page MB81ES123245-10 20 ■ BANK OPERATION COMMAND TABLE MINIMUM CLOCK LATENCY OR DELAY TIME FOR SINGLE BANK OPERATION ⎯ : Illegal Command *1 : If tRP (Min) < CL × tCK, minimum latency is a sum of (BL + CL) × tCK. *2 : Assume all banks are in Idle state. *3 : Assume output is in High-Z state. *4 : Assume tRAS (Min) is satisfied. *5 : Assume no I/O conflict. *6 : Assume after the last data have been appeared on DQ. *7 : If tRP (Min) < (CL − 1) × tCK, minimum latency is a sum of (BL + CL − 1) × tCK. MRS ACTV READ *4 READA WRIT *4 WRITA PRE PALL REF SELF BST MRS tRSC tRSC ⎯⎯ ⎯ ⎯ tRSC tRSC tRSC tRSC tRSC ACTV ⎯⎯ tRCD tRCD tRCD tRCD tRAS tRAS ⎯⎯ 1 READ ⎯⎯ 11 *5 1 *5 1 *4 1 *4 1 ⎯⎯ 1 READA *1, *2 BL + tRP BL + tRP ⎯⎯ ⎯ ⎯ *4 BL + tRP *4 BL + tRP *2 BL + tRP *2, *7 BL + tRP ⎯ WRIT ⎯⎯ tWR tWR 11 *4 tDPL *4 tDPL ⎯⎯ 1 WRITA *2 BL −1 + tDAL BL −1 + tDAL ⎯⎯ ⎯ ⎯ *4 BL −1 + tDAL *4 BL −1 + tDAL *2 BL −1 + tDAL *2 BL −1 + tDAL ⎯ PRE *2, *3 tRP tRP ⎯⎯ ⎯ ⎯ 1 *4 1 *2 tRP *2, *6 tRP 1 PALL *3 tRP tRP ⎯⎯ ⎯ ⎯ 11 tRP *6 tRP 1 REF tRC tRC ⎯⎯ ⎯ ⎯ tRC tRC tRC tRC tRC SELFX tRC tRC ⎯⎯ ⎯ ⎯ tRC tRC tRC tRC tRC Second command (same bank) First command |
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