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TCA6408 Datasheet(PDF) 6 Page - Texas Instruments

Part No. TCA6408
Description  LOW-VOLTAGE 8-BIT I2C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
Logo TI - Texas Instruments

TCA6408 Datasheet(HTML) 6 Page - Texas Instruments

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Data From
Shift Register
Write Configuration
Pulse
Write Pulse
Read Pulse
Write Polarity Pulse
Polarity
Inversion
Register
Input
Port
Register
Output
Port
Register
Configuration
Register
V
CCP
GND
Input Port
Register Data
Polarity
Register Data
ESD Protection Diode
P0 to P7
Output Port
Register Data
To INT
Q1
Q2
D
FF
C
K
Q
Q
D
FF
C
K
Q
Q
D
FF
C
K
Q
Q
D
FF
C
K
Q
Q
Data From
Shift Register
Data From
Shift Register
I/O Port
I2C Interface
TCA6408
LOW-VOLTAGE 8-BIT I2C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS
SCPS151C – FEBRUARY 2007 – REVISED JUNE 2007
Simplified Schematic of P0 to P7
A.
On power up or reset, all registers return to default values.
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The
input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled depending on the state of the output port register. In
this case, there are low impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on
the SDA input/output, while the SCL input is high (see Figure 1). After the start condition, the device address
byte is sent, MSB first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address input (ADDR) of the slave device must
not be changed between the start and the stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (start or stop) (see Figure 2).
6
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