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R2045S Datasheet(PDF) 14 Page - RICOH electronics devices division |
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R2045S Datasheet(HTML) 14 Page - RICOH electronics devices division |
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14 / 50 page  R2045S/D 14 The XST accepts the reading and writing of 0 and 1. The XST bit will be set to 0 when the oscillation halt sensing. The XST bit will hold 0 even after the restart of oscillation. (4) PON Power-on-reset Flag Bit PON Description 0 Normal condition 1 Detecting VDD power-on -reset (Default) The PON bit is for sensing power-on reset condition. * The PON bit will be set to 1 when VDD power-on from 0 volts. The PON bit will hold the setting of 1 even after power-on. * When the PON bit is set to 1, all bits will be reset to 0, in the Oscillation Adjustment Register, Control Register 1, and Control Register 2, except XST and PON. As a result, INTR pin stops outputting, and 32KOUT starts outputting. * The PON bit accepts only the writing of 0. Conversely, setting the PON bit to 1 causes no event. (5) CLEN1 32-kHz Clock Output Bit 1 CLEN1 Description 0 Enabling the 32-kHz clock output (Default) 1 Disabling the 32-kHz clock output Setting the CLEN1 bit or the CLEN2 bit (D4 in the control register 1) to 0 specifies generating clock pulses with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin. Conversely, setting both the CLEN1 and the CLEN2 bit to 1 specifies disabling (“H”) such output. (6) CTFG Periodic Interrupt Flag Bit CTFG Description 0 Periodic interrupt output = “H” (Default) 1 Periodic interrupt output = “L” The CTFG bit is set to 1 when the periodic interrupt signals are output from the INTR pin (“L”). The CTFG bit accepts only the writing of 0 in the level mode, which disables (“H”) the INTR pin until it is enabled (“L”) again in the next interrupt cycle. Conversely, setting the CTFG bit to 1 causes no event. (7) WAFG,DAFG Alarm_W Flag Bit and Alarm_D Flag Bit WAFG,DAFG Description 0 Indicating a mismatch between current time and preset alarm time (Default) 1 Indicating a match between current time and preset alarm time The WAFG and DAFG bits are valid only when the WALE and DALE have the setting of 1, which is caused approximately 61 µs after any match between current time and preset alarm time specified by the Alarm_W registers and the Alarm_D registers. The WAFG (DAFG) bit accepts only the writing of 0. INTR pin outputs off (“H”) when this bit is set to 0. And INTR pin outputs “L” again at the next preset alarm time. Conversely, setting the WAFG and DAFG bits to 1 causes no event. The WAFG and DAFG bits will have the reading of 0 when the alarm interrupt circuit is disabled with the WALE and DALE bits set to 0. The settings of the WAFG (DAFG) bit is synchronized with the output of the INTR pin as shown in the timing chart below. |
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