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RV5C386A Datasheet(PDF) 16 Page - RICOH electronics devices division

Part No. RV5C386A
Description  I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC WITH VOLTAGE MONITORING FUNCTION
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Manufacturer  RICOH [RICOH electronics devices division]
Direct Link  http://www.ricoh.com
Logo RICOH - RICOH electronics devices division

RV5C386A Datasheet(HTML) 16 Page - RICOH electronics devices division

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RV5C386A
16
WAFG, DAFG
Description
0
Indicating a mismatch between current time and preset alarm time
1
Indicating a match between current time and preset alarm time
2.2-7 WAFG and DAFG
Alarm_W Flag Bit and Alarm_D Flag Bit
(Default setting)
The WAFG and DAFG bits are valid only when the WALE and DALE bits have the setting of 1, which is caused
approximately 61µs after any match between current time and preset alarm time specified by the Alarm_W registers
and the Alarm_D registers. The WAFG and DAFG bits accept only the writing of 0, which disables (“H”) the INTRA
or INTRB pin until it is enabled (“L”) again at the next preset alarm time. Conversely, setting the WAFG and DAFG
bits to 1 causes no event. The WAFG and DAFG bits will have the reading of 0 when the alarm interrupt circuit is
disabled with the WALE and DALE bits set to 0. The settings of the WAFG and DAFG bits are synchronized with
the output of the INTRA and INTRB pins as shown in the timing chart below.
Output Relationships Between the WAFG or DAFG Bit and INTRA or INTRB
Writing of 0 to WAFG
(DAFG) bit
Writing of 0 to WAFG
(DAFG) bit
(Match between current time
and preset alarm time)
(Match between current time
and preset alarm time)
(Match between current time
and preset alarm time)
Settings of WAFG (DAFG) bit
Output of INTRB (INTRA) pin
Approx.61
µs
Approx.61
µs
CTFG
Description
0
Periodic interrupt output “H” (OFF)
1
Periodic interrupt output “L” (ON)
2.2-6 CTFG
Periodic Interrupt Flag Bit
(Default setting)
The CTFG bit is set to 1 when the periodic interrupt signals are output from the INTRA pin (“L”). The CTFG bit
accepts only the writing of 0 in the level mode, which disables (“H”) the INTRA pin until it is enabled (“L”) again in
the next interrupt cycle. Conversely, setting the CTFG bit to 1 causes no event.


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