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SST36VF1601-70-4C-BK Datasheet(PDF) 2 Page - Silicon Storage Technology, Inc |
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SST36VF1601-70-4C-BK Datasheet(HTML) 2 Page - Silicon Storage Technology, Inc |
2 / 26 page 2 © 2000 Silicon Storage Technology, Inc. 16 Megabit Concurrent SuperFlash SST36VF1601 / SST36VF1602 Advance Information S71142 373-3 11/00 gies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST36VF1601/1602 are offered in 48-pin TSOP and 48- ball TFBGA packages. See Figures 3 and 4 for pinouts. Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. The SST36VF1601/1602 also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current to typically 4 µA. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another read cycle, with no access time penalty. Concurrent Read/Write Operation Dual bank architecture of SST36VF1601/1602 devices allows the Concurrent Read/Write operation whereby the user can read from one bank while program or erase in the other bank. This operation can be used when the user needs to read system code in one bank while updating data in the other bank. CONCURRENT READ/WRITE STATE TABLE Bank 1 Bank 2 Read No Operation Read Write Write Read Write No Operation No Operation Read No Operation Write Note: For the purposes of this table, write means to Block-, Sector-, or Chip-Erase, or Word-Program as applicable to the appropriate bank. Read The Read operation of the SST36VF1601/1602 is con- trolled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 5). Word-Program Operation The SST36VF1601/1602 are programmed on a word-by- word basis. The Program operation consists of three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initi- ated, will be completed within 10 µs. See Figures 6 and 7 for WE# and CE# controlled Program operation timing dia- grams and Figure 19 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. Sector- (Block-) Erase Operation The Sector- (Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-by-block) basis. The SST36VF1601/1602 offer both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 1 KWord. The Block-Erase mode is basedonuniformblocksizeof32KWord.TheSector-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. See Figures 11 and 12 for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored. Chip-EraseOperation The SST36VF1601/1602 provide a Chip-Erase operation, which allows the user to erase all unprotected sectors/ blocks to the “1” state. This is useful when the device must be quickly erased. The Chip-Erase operation is initiated by executing a six- byte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or |
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