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SKY65006 Datasheet(PDF) 7 Page - Skyworks Solutions Inc.

Part No. SKY65006
Description  3.3 V, 2.5 GHz Linear Power Amplifier
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Maker  SKYWORKS [Skyworks Solutions Inc.]
Homepage  http://www.skyworksinc.com
Logo SKYWORKS - Skyworks Solutions Inc.

SKY65006 Datasheet(HTML) 7 Page - Skyworks Solutions Inc.

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PRELIMINARY DATA SHEET • SKY65006
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
200122 Rev. D • Skyworks Proprietary Information. • Products and product information are subject to change without notice. • May 14, 2007
7
Application Information
The Skyworks SKY65006 is a high-performance 2-stage InGaP
power amplifier designed for 2.4–2.5 GHz ISM, IEEE802.11b and
802.11g WLAN band applications. The SKY65006 is a high-effi-
ciency linear amplifier designed for single 3.3 V supply operation,
requiring no input and output matching components for 50
operation. This device also includes an internal power detector
and integrated harmonic filter for reduced PC board component
count. The integrated low pass filter is also highly effective in
reducing harmonics at their source by localizing harmonic rejec-
tion to a tiny portion of the PA chip. This significantly reduces the
risk of radiation from a high order filter design external to the
amplifier. Filtering of harmonics in this way may eliminate the
need for an external shield over the PA, and reduces overall cost.
If additional suppression of harmonics is required, an external
low pass function can be added to the output of the amplifier.
Refer to data sheet for filter values and response plots.
The SKY65006 requires a nominal VCC supply voltage of 3.3 V
and a positive control voltage VREG1, 2 providing bias for the first
and second stage amplifiers. Nominal control voltage, VREG, is
2.5–2.6 V resulting from the stack of two emitter-base junctions
of about 1.3 V each for typical GaAs HBT device. To insure proper
reference currents into VREG1, 2, for normal operation of the RF
stages, drop-in resistors could be used between VREG1, 2 and a
VREG supply. Bias control would then be set in the range of
2.7–3.5 V allowing added flexibility for both the control voltage
value and desired RF stage currents. If additional output power is
required, VCC can also be increased 4.0 V. Biasing of each stage
consists of an external resistor of 180
Ω (R1) and 240 Ω (R2) for
the recommended typical bias currents of 15 mA and 35 mA for
stage 1 and 2 respectively. In most applications one end of each
of the bias resistors is tied to the VREG supply, so both amplifier
stages are biased with a single common voltage. Capacitor C4,
1.8 pF, bypasses the VREG stage 1 control bias pin and is used to
improve RF rejection of the bias control lines.
Although there is no need for external matching when operating
in a 50
Ω system, an input and output 6 pF decoupling capacitor
is shown on the evaluation circuit. This capacitor is only manda-
tory on the RF output side of the device. The RF input is DC
isolated and could be connected to driver circuits directly without
the need for additional blocking capacitors. Capacitors of 6 pF
were chosen because their self-resonant frequency would not
add any unwanted disturbances in the 50
Ω transmission line
path. The SKY65006 is unconditionally stable at any frequency
and voltage setting as long as it is grounded correctly. It is
extremely important to pay special attention to all RF grounding
pads especially those directly under the device. Ground pad vias
and solder mask patterns are designed in such a way to ensure
minimum parasitic inductance to the underlying ground and at
each RF bypassing component. To ensure reliable soldering of the
device paddle, it is highly recommended that filled vias with a
minimal reliable diameter and filling the entire pattern
be used. The filled-via technique would remove the possibility of
solder migration down via holes, which can cause a large
increase in inductance and possible instabilities.
Each amplifier stage is biased through a series choke and shunt
capacitor combination which is completely integrated on chip to
provide maximum RF isolation and harmonic radiation immunity.
To avoid interferences from the low-frequency gain of the ampli-
fier and to insure stability at low out of band frequencies, stage
1 amplifier is biased through inductor L1. It is also then shunted
by a large value capacitance to ensure proper low-frequency
bypassing of the amplifier. To avoid a shunting effect on the
50
Ω line, a high-impedance, self-resonating choke L2 (in the
range of 22–33 nH depending on vendor and size) and a large
value bypass capacitor are used for biasing the output stage.
Capacitor C7, 4.7 µF, on the VCC line should be placed as close
as possible to the biasing network supplying stage 2 or the
output stage of the amplifier. Applications with the DC bias being
generated strictly from a battery as the voltage source may not
require this capacitor, or as large a value as specified in the
applications circuit. However, in that case, a smaller ceramic
capacitor of at least 0.1 µF should be used and also placed as
close as possible to the biasing network supplying stage 2.
Note: Normal operation requires that VCC including VBCC be
applied before the application of the VREG voltages biasing stage
1 and 2 bias currents. If VCC and VBCC are not applied prior to
the application of the VREG biasing, voltage damage could occur
from excessive base current draw through the collector junction
of the bias transistor.
The SKY65006 also includes an on-board, compensated power
detector providing a single-ended output voltage for measuring
power over a wide dynamic range. The detector load and
settling time constant are set external to the device. Nominal
detector load is 51K
Ω and 5 pF, yielding a settling time of
approximately 500 ns. Note that there is an internal 5 pF on-chip
capacitance, so the net capacitance value is approximately 10 pF.
Lower resistor values may be used if necessary with the net
impact being a lower output detector voltage over its useful
dynamic range. For proper detector operation, a reference voltage
must be applied to the VDET line. Any voltage between 2 and 4 V
is acceptable for the reference voltage, but it is recommended to
supply VDET from the VREG power supply. The benefit in doing
this is that the approximate 2 mA of current that the reference
circuit consumes will not be wasted with the PA in the “Off”
state. There is also the option of not biasing the detector refer-
ence at all if the current consumption is of prime importance.
The detector will then act as a normal unbiased detector, and
sensitivity and accuracy will be degraded.


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