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SI5368B-B-GQ Datasheet(PDF) 10 Page - Silicon Laboratories |
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SI5368B-B-GQ Datasheet(HTML) 10 Page - Silicon Laboratories |
10 / 18 page Si5368 10 Preliminary Rev. 0.3 32 42 RATE1 RATE0 I 3-Level External Crystal or Reference Clock Rate. Three level inputs that select the type and rate of external crys- tal or reference clock to be applied to the XA/XB port. Settings: HH = No Crystal or Reference Clock. Converts part to a Si5367 device. See Si5367 Data Sheet for operation. (Wideband). MM = 114.285 MHz 3rd OT crystal (Narrowband). LM = 38.88 MHz external clock (Narrowband). All others = Reserved. 34 35 CKIN2+ CKIN2– IMULTI Clock Input 2. Differential input clock. This input can also be driven with a sin- gle-ended signal. 39 40 CKIN3+ CKIN3– IMULTI Clock Input 3. Differential clock input. This input can also be driven with a sin- gle-ended signal. CKIN3 serves as the frame sync input associ- ated with the CKIN1 clock when CK_CONFIG_REG =1. 44 45 CKIN1+ CKIN1– IMULTI Clock Input 1. Differential clock input. This input can also be driven with a sin- gle-ended signal. 49 LOL O LVCMOS PLL Loss of Lock Indicator. This pin functions as the active high PLL loss of lock indicator if the LOL_PIN register bit is set to one. 0 = PLL locked. 1 = PLL unlocked. If LOL_PIN = 0, this pin will tristate. Active polarity is controlled by the LOL_POL bit. The PLL lock status will always be reflected in the LOL_INT read only register bit. 54 DEC I LVCMOS Coarse Latency Decrement. A pulse on this pin decreases the input to output device latency by 1/fOSC (approximately 200 ps). Detailed operations and tim- ing characteristics for this pin may be found in the Any-Rate Precision Clock Family Reference Manual. There is no limit on the range of latency adjustment by this method. Pin control is enabled by setting INCDEC_PIN = 1 (default). If INCDEC_PIN = 0, this pin is ignored and coarse output latency is controlled via the CLAT register. If both INC and DEC are tied high, phase buildout is disabled and the device maintains a fixed-phase relationship between the selected input clock and the output clock during an input clock switch. Detailed operations and timing characteristics for these pins may be found in the Any-Rate Precision Clock Fam- ily Reference Manual. This pin has a weak pull-down. Table 3. Si5368 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level Description Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map. |
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