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SI5325B-B-GM Datasheet(PDF) 2 Page - Silicon Laboratories |
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SI5325B-B-GM Datasheet(HTML) 2 Page - Silicon Laboratories |
2 / 14 page Si5325 2 Preliminary Rev. 0.26 Table 1. Performance Specifications (VDD = 1.8, 2.5, or 3.3 V ±10%, TA = –40 to 85 ºC) Parameter Symbol Test Condition Min Typ Max Unit Temperature Range TA –40 25 85 ºC Supply Voltage VDD 2.97 3.3 3.63 V 2.25 2.5 2.75 V 1.62 1.8 1.98 V Supply Current IDD fOUT = 622.08 MHz Both CKOUTs enabled LVPECL format output — 251 279 mA CKOUT2 disabled — 217 243 mA fOUT = 19.44 MHz Both CKOUTs enabled CMOS format output — 204 234 mA CKOUT2 disabled — 194 220 mA Tristate/Sleep Mode — TBD TBD mA Input Clock Frequency (CKIN1, CKIN2) CKF Input frequency and clock multiplication ratio deter- mined by programming device PLL dividers. Consult Silicon Laboratories configu- ration software DSPLLsim at www.silabs.com/timing to determine PLL divider set- tings for a given input fre- quency/clock multiplication ratio combination. 10 — 710 MHz Output Clock Frequency (CKOUT1, CKOUT2) CKOF 10 970 1213 — — — 945 1134 1417 MHz Input Clocks (CKIN1, CKIN2) Differential Voltage Swing CKNDPP 0.25 — 1.9 VPP Common Mode Voltage CKNVCM 1.8 V ±10% 0.9 — 1.4 V 2.5 V ±10% 1.0 — 1.7 V 3.3 V ±10% 1.1 — 1.95 V Rise/Fall Time CKNTRF 20–80% — 11 ns Duty Cycle CKNDC Whichever is less 40 — 60 % 50 — — ns Output Clocks (CKOUT1, CKOUT2) Common Mode VOCM LVPECL 100 Ω load line-to-line VDD –1.42 — VDD –1.25 V Differential Output Swing VOD 1.1 — 1.9 V Single Ended Output Swing VSE 0.5 — 0.93 V Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing. |
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