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C8051T605-GM Datasheet(PDF) 7 Page - Silicon Laboratories |
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C8051T605-GM Datasheet(HTML) 7 Page - Silicon Laboratories |
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7 / 168 page  Rev. 0.5 7 C8051T600/1/2/3/4/5 List of Figures 1. System Overview Figure 1.1. C8051T600/2/4 Block Diagram .............................................................. 15 Figure 1.2. C8051T601/3/5 Block Diagram .............................................................. 15 Figure 1.3. On-Chip Clock and Reset ...................................................................... 17 Figure 1.4. On-chip Memory Map (C8051T600/1 shown) ........................................ 18 Figure 1.5. Digital Crossbar Diagram ....................................................................... 19 Figure 1.6. PCA Block Diagram ............................................................................... 20 Figure 1.7. PCA Block Diagram ............................................................................... 20 Figure 1.8. 10-Bit ADC Block Diagram..................................................................... 21 Figure 1.9. Comparator Block Diagram.................................................................... 22 2. Absolute Maximum Ratings 3. Global Electrical Characteristics 4. Pinout and Package Definitions Figure 4.1. QFN-11 Pinout Diagram (Top View) ...................................................... 27 Figure 4.2. QFN-11 Package Drawing ..................................................................... 28 Figure 4.3. SOIC-14 Pinout Diagram (Top View) ..................................................... 29 Figure 4.4. SOIC-14 Package Drawing .................................................................... 30 5. ADC0 - 10-Bit SAR ADC (C8051T600/2/4 Only) Figure 5.1. ADC0 Functional Block Diagram............................................................ 31 Figure 5.2. Temperature Sensor Transfer Function ................................................. 33 Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.4 V) ....... 34 Figure 5.4. ADC Tracking and Conversion Timing................................................... 37 Figure 5.5. ADC0 Equivalent Input Circuits.............................................................. 38 Figure 5.6. ADC Window Compare Examples ......................................................... 42 6. Voltage Reference Options Figure 6.1. Voltage Reference Functional Block Diagram ....................................... 45 7. Comparator0 Figure 7.1. Comparator0 Functional Block Diagram ................................................ 47 Figure 7.2. Comparator Hysteresis Plot ................................................................... 48 8. Voltage Regulator (REG0) 9. CIP-51 Microcontroller Figure 9.1. CIP-51 Block Diagram............................................................................ 55 Figure 9.2. Program Memory Maps.......................................................................... 61 Figure 9.3. Data Memory Map.................................................................................. 62 10. Reset Sources Figure 10.1. Reset Sources...................................................................................... 81 Figure 10.2. Power-On and VDD Monitor Reset Timing ........................................... 82 11. One-Time Programmable Read-Only Memory Figure 11.1. OTP EPROM Program Memory Map ................................................... 88 12. Oscillators Figure 12.1. Oscillator Diagram................................................................................ 91 13. Port Input/Output Figure 13.1. Port I/O Functional Block Diagram ....................................................... 97 |
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