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PS51259-A Datasheet(PDF) 6 Page - Mitsubishi Electric Semiconductor

Part No. PS51259-A
Description  Single phase AC input, DC output IGBT/FWD converter
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Maker  MITSUBISHI [Mitsubishi Electric Semiconductor]
Homepage  http://www.mitsubishichips.com
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PS51259-A Datasheet(HTML) 6 Page - Mitsubishi Electric Semiconductor

   
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MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
PS51259-A
TRANSFER-MOLD TYPE
INSULATED TYPE
Mar. 2003
DIP-PFC Wiring Guidelines
Because DIP-PFC switches large current at a very high speed, considerable large surge voltage is generated easily between P and N termi-
nals. Please pay attention to the following items:
• The area of P-Co-N shown in Fig. 3 should be as small as possible because the rectangle shaped switching current flows on this route. In
addition, please add a bypass condenser Co’ with good frequency response such as a polypropylene film condenser closely to the P and N
terminals.
• The two IGBT emitters are connected to the VNO terminal of LVIC inside the DIP-PFC. If the internal wiring inductance shown as L1 and L2
in Fig. 4 is too large, large surge voltage will be generated by di/dt. Especially, the lower the temperature, the faster the switching speed,
therefore the larger the di/dt. This surge voltage applies to the VNO and N terminals, which is possible to destruct LVIC.
• In order to suppress the surge voltage, the external wiring method shown in Fig. 4 is recommended. To reduce the parasitic wiring induc-
tance, the wiring of the external terminals of N(N-1) and N(N-2) should be made as short as possible.
• Please mount a fast clamp diode (EG01Y@Sanken) between N and control GND terminals to prevent control GND potential variation from
the minus voltage of N terminal.
R
N / F
LVIC
VNO
P
DIP PFC
S
VIN
N2
N
(N-1, N-2)
Control IC
MCU
VD
GND
Co'
Co
+
P
S
+
+
R
N-1
L1
L2
GND
VD
Control input
GND
VD
VIN
N2
N2
N-2
Insert a diode here
To restrain the IPM surge voltage,
mount the condenser closely to the
terminals
To reduce the parasitic inductance,
this wire should close to N terminal
Fig. 3 DIP-PFC INTERFACE
Fig. 4 RECOMMENDED WIRING METHOD


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