RM5231A-300-HI datasheet(9/40 Pages) PMC

Part #	RM5231A-300-HI

Description	RM5231A??Microprocessor with 32-Bit System Bus Data Sheet Preliminary

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Manufacturer	PMC [PMC-Sierra, Inc]

Direct Link	http://www.pmc-sierra.com

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9 / 40 page

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

9

Document ID: PMC-2002174, Issue 2

RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet

Preliminary

1

Features

•

Dual Issue superscalar microprocessor

•

250, 300, and 350 MHz operating frequencies

•

Up to 420 Dhrystone 2.1 MIPS

•

System interface optimized for embedded applications

•

32-bit system interface lowers total system cost

•

High-performance write protocols maximize uncached write bandwidth

•

Processor clock multipliers: 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9

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IEEE 1149.1 JTAG boundary scan

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Integrated on-chip caches

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32 KB instruction and 32 KB data — 2 way set associative

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Per set locking

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Virtually indexed, physically tagged

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Write-back and write-through on a per page basis

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Pipeline restart on first doubleword for data cache misses

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Integrated memory management unit

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Fully associative joint TLB (shared by I and D translations)

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48 dual entries map 96 pages

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Variable page size (4 KB to 16 MB in 4x increments)

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High-performance floating-point unit — up to 700 MFLOPS

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Single cycle repeat rate for common single-precision operations and some double pre-

cision operations

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Two cycle repeat rate for double-precision multiply and double precision combined

multiply-add operations

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Single cycle repeat rate for single-precision combined multiply-add operation

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MIPS IV instruction set

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Floating point multiply-add instruction increases performance in signal processing

and graphics applications

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Conditional moves to reduce branch frequency

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Index address modes (register + register)

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Embedded application enhancements

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Specialized DSP integer Multiply-Accumulate instructions and 3-operand multiply

instruction

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I and D cache locking by set

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Optional dedicated exception vector for interrupts

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Fully static 0.18 micron CMOS design with power down logic

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Standby reduced power mode with WAIT instruction

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1.65 V or 1.8 V core with 3.3 V or 2.5 V I/O

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128-pin QFP package

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RM5231A-300-HI Datasheet(PDF) 9 Page - PMC-Sierra, Inc

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