Electronic Components Datasheet Search |
|
RM5231A-300-HI Datasheet(PDF) 9 Page - PMC-Sierra, Inc |
|
RM5231A-300-HI Datasheet(HTML) 9 Page - PMC-Sierra, Inc |
9 / 40 page Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use 9 Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet Preliminary 1 Features • Dual Issue superscalar microprocessor • 250, 300, and 350 MHz operating frequencies • Up to 420 Dhrystone 2.1 MIPS • System interface optimized for embedded applications • 32-bit system interface lowers total system cost • High-performance write protocols maximize uncached write bandwidth • Processor clock multipliers: 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9 • IEEE 1149.1 JTAG boundary scan • Integrated on-chip caches • 32 KB instruction and 32 KB data — 2 way set associative • Per set locking • Virtually indexed, physically tagged • Write-back and write-through on a per page basis • Pipeline restart on first doubleword for data cache misses • Integrated memory management unit • Fully associative joint TLB (shared by I and D translations) • 48 dual entries map 96 pages • Variable page size (4 KB to 16 MB in 4x increments) • High-performance floating-point unit — up to 700 MFLOPS • Single cycle repeat rate for common single-precision operations and some double pre- cision operations • Two cycle repeat rate for double-precision multiply and double precision combined multiply-add operations • Single cycle repeat rate for single-precision combined multiply-add operation • MIPS IV instruction set • Floating point multiply-add instruction increases performance in signal processing and graphics applications • Conditional moves to reduce branch frequency • Index address modes (register + register) • Embedded application enhancements • Specialized DSP integer Multiply-Accumulate instructions and 3-operand multiply instruction • I and D cache locking by set • Optional dedicated exception vector for interrupts • Fully static 0.18 micron CMOS design with power down logic • Standby reduced power mode with WAIT instruction • 1.65 V or 1.8 V core with 3.3 V or 2.5 V I/O • 128-pin QFP package |
Similar Part No. - RM5231A-300-HI |
|
Similar Description - RM5231A-300-HI |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |