RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet

Preliminary

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

5

Document ID: PMC-2002174, Issue 2

Table of Contents

Legal Information ...........................................................................................................................2

Revision History .............................................................................................................................3

Document Conventions .................................................................................................................4

Table of Contents ..........................................................................................................................5

List of Figures ................................................................................................................................7

List of Tables .................................................................................................................................8

1

Features ..................................................................................................................................9

2

Block Diagram .......................................................................................................................10

3

Hardware Overview ...............................................................................................................11

3.1

Superscalar Dispatch ...................................................................................................11

3.2

CPU Registers .............................................................................................................11

3.3

Pipeline ........................................................................................................................11

3.4

Integer Unit ..................................................................................................................12

3.5

Register File .................................................................................................................12

3.6

ALU ..............................................................................................................................12

3.7

Integer Multiply/Divide ..................................................................................................12

3.8

Floating-Point Co-Processor ........................................................................................13

3.9

Floating-Point Unit .......................................................................................................13

3.10 Floating-Point General Register File ............................................................................15

3.11 System Control Coprocessor (CP0) .............................................................................16

3.12 System Control Co-Processor Registers .....................................................................16

3.13 Virtual to Physical Address Mapping ............................................................................17

3.14 Joint TLB ......................................................................................................................18

3.15 Instruction TLB .............................................................................................................19

3.16 Data TLB ......................................................................................................................19

3.17 Cache Memory .............................................................................................................19

3.18 Instruction Cache .........................................................................................................19

3.19 Data Cache ..................................................................................................................20

3.20 Write Buffer ..................................................................................................................21

3.21 System Interface ..........................................................................................................22

3.22 System Address/Data Bus ...........................................................................................22

3.23 System Command Bus ................................................................................................22

3.24 Handshake Signals ......................................................................................................23

3.25 Non-overlapping System Interface ...............................................................................23

3.26 Enhanced Write Modes ................................................................................................24

3.27 External Requests ........................................................................................................25

3.28 Interrupt Handling ........................................................................................................25

3.29 Standby Mode ..............................................................................................................25

3.30 JTAG Interface .............................................................................................................25