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PM8621-BIAP Datasheet(PDF) 5 Page - PMC-Sierra, Inc |
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PM8621-BIAP Datasheet(HTML) 5 Page - PMC-Sierra, Inc |
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5 / 184 page  NSE-8G™ Standard Product Data Sheet Preliminary Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 4 Document ID: PMC-2010850, Issue 1 9.9.1 In-Band Signaling Channel Fixed Overhead........................................52 9.10 Microprocessor Interface ..................................................................................53 10 Normal Mode Register Description............................................................................57 11 Test Features Description........................................................................................125 11.1 Master Test and Test Configuration Registers ................................................125 11.2 JTAG Test Port ................................................................................................127 11.2.1 Boundary Scan Cells..........................................................................131 12 Operation .................................................................................................................134 12.1 Software Default Settings ...............................................................................134 12.1.1 Setting the T8TE Time-slot Configuration #1 Register.......................134 12.1.2 Setting the T8TE Time-slot Configuration #2 Register.......................134 12.1.3 Configuring the NSE-8G to Use Fewer Links ....................................134 12.1.4 PCB Design Notes .............................................................................136 12.2 “C1” Synchronization.......................................................................................136 12.3 Synchronized Control Setting Changes ..........................................................137 12.3.1 SBS/NSE-8G Systems with DS0 and CAS Switching .......................137 12.3.2 SBS/NSE-8G Systems Switching DS0s without CAS........................139 12.3.3 SBS/NSE-8G non-DS0 Level Switching with SBI336 Devices ..........141 12.4 NSE-8G CPU Interaction with the Switching Cycle When Using the ILC.......142 12.5 Controlling Frame Alignment in the Receive Port ...........................................143 12.6 DS0 Cross-Bar Switch (DCB) Operation ........................................................144 12.6.1 Configuring the DCB using Port Transfer Mode.................................144 12.6.2 Configuring the DCB using Word transfer mode:...............................145 12.6.3 Reading Configurations......................................................................146 12.6.4 DCB Online to Offline Memory Page Copy........................................146 12.7 Telecombus Mode Operation ..........................................................................147 12.8 SBI Column Mode Operation ..........................................................................147 12.9 SBI DS0 Mode Operation ...............................................................................148 12.10 SBI DS0 with CAS Mode Operation................................................................148 12.11 ILC Operation..................................................................................................149 12.12 ILC CPU Operations .......................................................................................149 12.12.1 Accessing the Transmit Message FIFO .............................................149 12.12.2 Accessing the Receive Message FIFO ..............................................150 12.12.3 Handling the Transmit Header ...........................................................153 12.12.4 Handling the Receive Header ............................................................154 |
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