IBIS5-B-1300 CYII5FM1300AB
Document #: 38-05710 Rev. *C
Page 5 of 40
The VDDR_RIGHT voltage is generated from the VDDR_LEFT
voltage
using
a
circuit
that
is
programmed
with
the
KNEEPOINT_LSB/MSB bits in the sequencer register (see also
“Pixel reset knee-point for multiple slope operation (bits 8, 9, and
10).” on page 14). You can disconnect the VDDR_RIGHT pin
from the circuit and apply an external voltage to supply the
multiple slope reset voltage by setting the VDDR_RIGHT_EXT
bit in the SEQUENCER register. When no external voltage is
applied (recommended), connect the VDDR_RIGHT pin to a
capacitor (recommended value = 1µF). VDDC is the pixel core
supply. VDDA is the image core and periphery analog supply.
VDDD is the image core and periphery digital supply.
Note that the IBIS5-B-1300 image sensor has no on-chip power
rejection circuitry. As a consequence all variations on the analog
supply voltages can contribute to random variations (noise) on
the analog pixel signal, which is seen as random noise in the
image. During the camera design, take precautions to supply the
sensor with very stable supply voltages to avoid this additional
noise. The pixel array (VDDR_LEFT, VDDH and VDDC) analog
supplies are especially vulnerable to this.
Snapshot Shutter Supply Considerations
The recommended supply voltage settings listed in Table 3 are
used when the IBIS5-B-1300 sensor is in snapshot shutter mode
only.
Dual Shutter Supply Considerations
If you analyze the supply settings listed in Table 3, you can see
some fixed column non-uniformities (FPN) when operating in
rolling shutter mode. If a dual shutter mode (both rolling and
snapshot shutter) is required during operation, you must apply
the supply settings listed in Table 4 to achieve the best possible
image quality.
Image Core Biasing Signals
Table 5 summarizes the biasing signals required to drive the
IBIS5-A-1300. For optimizations reasons, with respect to speed
and power dissipation of all internal blocks, several biasing
resistors are needed.
Each biasing signal determines the operation of a corresponding
module in the sense that it controls the speed and power dissi-
pation. The tolerance on the DC-level of the bias levels can vary
±150 mV due to process variations.
Table 3.
Snapshot Shutter Recommended Supply Settings
Parameter
Description
Typ
Unit
VDDH
Voltage on HOLD switches.
+4.5
V
VDDR_LEFT
Highest reset voltage.
+4.5
V
VDDC
Pixel core voltage.
+3.3
V
VDDA
Analog supply voltage of the
image core.
+3.3
V
VDDD
Digital supply voltage of the
image core.
+3.3
V
GNDA
Analog ground.
0
V
GNDD
Digital ground.
0
V
GND_AB
Anti-blooming ground.
0
V
Table 4.
Dual Shutter Recommended Supply Settings
Parameter
Description
Typ
Unit
VDDH
Voltage on HOLD switches.
+4.5
V
VDDR_LEFT
Highest reset voltage.
+4.5
V
VDDC
Pixel core voltage.
+3.0
V
VDDA
Analog supply voltage of the
image core.
+3.3
V
VDDD
Digital supply voltage of the
image core.
+3.3
V
GNDA
Analog ground.
0
V
GNDD
Digital ground.
0
V
GND_AB
Anti-blooming ground.
0
V
Table 5.
Overview of Bias Signals
Signal
Comment
Related module
DC-Level
DEC_CMD
Connect to VDDA with R = 50 k
Ω and decouple to GNDA with C = 100 nF. Decoder stage.
1.0V
DAC_VHIGH
Connect to VDDA with R = 0
Ω.
High level of DAC.
3.3V
DAC_VLOW
Connect to GNDA with R = 0
Ω.
Low level of DAC.
0.0V
AMP_CMD
Connect to VDDA with R = 50 k
Ω and decouple to GNDA with C = 100 nF. Output amplifier stage.
1.2V
COL_CMD
Connect to VDDA with R = 50 k
Ω and decouple to GNDA with C = 100 nF. Columns amplifiers stage.
1.0V
PC_CMD
Connect to VDDA with R = 25 k
Ω and decouple to GNDA with C = 100 nF. Pre-charge of column
busses.
1.1V
ADC_CMD
Connect to VDDA with R = 50 k
Ω and decouple to GNDA with C = 100 nF. Analog stage of ADC.
1.0V
ADC_VHIGH
Connect to VDDA with R = 360
Ω and decouple to GNDA with C = 100 nF. High level of ADC.
2.7V
ADC_VLOW
Connect to GNDA with R = 1200
Ω and decouple to GNDA with C = 100 nF. Low level of ADC.
1.8V