IBIS5-B-1300 CYII5FM1300AB
Document #: 38-05710 Rev. *C
Page 8 of 40
Analog to Digital Converter
The IBIS5-B-1300 has a 10-bit flash analog digital converter
running nominally at 40 Msamples/s. The ADC is electrically
separated from the image sensor. Tie the input of the ADC
(ADC_IN; pin 69) externally to the output (PXL_OUT1; pin 28) of
the output amplifier.
ADC Timing
At the rising edge of SYS_CLOCK, the next pixel is fed to the
input of the output amplifier. Due to internal delays of the
SYS_CLOCK signal, it takes approximately 20 ns before the
output amplifier outputs the analog value of the pixel as shown
in Figure 10 on page 9.
The ADC converts the pixel data on the rising edge of the
ADC_CLOCK, but it takes two clock cycles before this pixel data
is at the output of the ADC. Figure 10 shows this pipeline delay.
A
GAIN [0…3]
unity gain
1
S
R
S
R
odd
even
+
+
DAC_VHIGH
DAC_VLOW
DAC_RAW [6:0]
DAC_FINE [6:0]
DAC_RAW
DAC_FINE
PXL_OUT
Figure 8. Output Structure
RDAC_VHIGH
DAC_VLOW = 0V
DAC_VHIGH = 3.3V
RDAC_VLOW
RDAC
external
internal
external
7.88 k
Ω
internal
Figure 9. In- and External DAC Connections
Table 9.
ADC Specifications
Input range
1–3V[1]
Quantization
10 Bits
Nominal data rate
40 Msamples/s
DNL (linear conversion mode)
Typ. < 0.5 LSB
INL (linear conversion mode)
Typ. < 3 LSB
Input capacitance
< 20 pF
Power dissipation @ 40 MHz
Typ. 45 mA * 3.3V = 150 mW
Conversion law
Linear / Gamma-corrected
Note
1. The internal ADC range is typically 100 mV lower then the external applied ADC_VHIGH and ADC_VLOW voltages due to voltage drops over parasitic internal resistors