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PM7383 Datasheet(PDF) 88 Page - PMC-Sierra, Inc |
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PM7383 Datasheet(HTML) 88 Page - PMC-Sierra, Inc |
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88 / 231 page  RELEASED PM7383 FREEDM-32A256 DATASHEET PMC-2010336 ISSUE 1 FRAME ENGINE AND DATA LINK MANAGER 32A256 PROPRIETARY AND CONFIDENTIAL 80 Register 0x010 : FREEDM-32A256 Master Link Activity Monitor Bit Type Function Default Bit 15 R TLGA[7] X Bit 14 R TLGA[6] X Bit 13 R TLGA[5] X Bit 12 R TLGA[4] X Bit 11 R TLGA[3] X Bit 10 R TLGA[2] X Bit 9 R TLGA[1] X Bit 8 R TLGA[0] X Bit 7 R RLGA[7] X Bit 6 R RLGA[6] X Bit 5 R RLGA[5] X Bit 4 R RLGA[4] X Bit 3 R RLGA[3] X Bit 2 R RLGA[2] X Bit 1 R RLGA[1] X Bit 0 R RLGA[0] X This register provides activity monitoring on FREEDM-32A256 receive and transmit link inputs. When a monitored input makes a low to high transition, the corresponding register bit is set high. The bit will remain high until this register is read, at which point, all the bits in this register are cleared. A lack of transitions is indicated by the corresponding register bit reading low. This register should be read periodically to detect for stuck at conditions. RLGA[0]: The receive link group #0 active bit (RLGA[0]) monitors for transitions on the RD[3:0] and RCLK[3:0]/RMVCK[0]/RMV8DC inputs. RLGA[0] is set high when either: 1. Each of RD[3:0] has been sampled low and sampled high by rising edges of the corresponding RCLK[3:0] inputs, or |
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