5 / 45 page
CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
Document #: 38-02065 Rev. *F
Page 5 of 45
INA1+
INA1–
INA2+
INA2–
INSELA
INB1+
INB1–
INB2+
INB2–
INSELB
INC1+
INC1–
INC2+
INC2–
INSELC
IND1+
IND1–
IND2+
IND2–
INSELD
Clock &
Data
Recovery
PLL
Clock &
Data
Recovery
PLL
Clock &
Data
Recovery
PLL
Clock &
Data
Recovery
PLL
LFID
LFIC
LFIB
LFIA
8
RXSTC[2:0]
RXDC[7:0]
3
8
RXSTB[2:0]
RXDB[7:0]
3
8
RXSTD[2:0]
RXDD[7:0]
3
8
RXSTA[2:0]
RXDA[7:0]
3
Receive
Signal
Monitor
Receive
Signal
Monitor
Receive
Signal
Monitor
Receive
Signal
Monitor
RXCLKD+
RXCLKD–
÷2
RXCLKC+
RXCLKC–
÷2
RXCLKB+
RXCLKB–
÷2
RXCLKA+
RXCLKA–
÷2
RXRATE[A..D]
FRAMCHAR[A..D]
RFEN[A..D]
SDASELA[1:0]
JTAG
Boundary
Scan
Controller
TDO
TMS
TCLK
TDI
Clock
Select
Clock
Select
Clock
Select
Clock
Select
RXCKSEL[A..D]
RESET
Receive Path Block Diagram
=
Internal Signal
RXPLLPDA
RFMODE[A..D][1:0]
LPENA
RXBIST[A..D]
DECMODE[A..D]
LPENB
LPENC
LPEND
TRST
SDASELB[1:0]
RXPLLPDB
SDASELC[1:0]
RXPLLPDC
SDASELD[1:0]
RXPLLPDD
DECBYP[A..D]
SPDSELA
SPDSELB
SPDSELC
SPDSELD
ULCB
ULCA
ULCC
ULCD
LDTDEN
TXLBD
TXLBC
TXLBB
TXLBA
TXLB[A..D] are Internal Serial Loopback Signals
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