Document #: 38-06069 Rev. *I
Page 11 of 25
CYD04S72V
CYD09S72V
CYD18S72V
Maximum Ratings[22]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied............................................–55°C to + 125°C
Supply Voltage to Ground Potential .............. –0.5V to + 4.6V
DC Voltage Applied to
Outputs in High-Z State..........................–0.5V to VDD + 0.5V
DC Input Voltage...............................–0.5V to VDD + 0.5V[23]
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... > 2000V
(JEDEC JESD22-A114-2000B)
Latch-up Current..................................................... > 200 mA
Operating Range
Range
Ambient
Temperature
VDD
VCORE[11]
Commercial
0°C to +70°C 3.3V ± 165 mV 1.8V ± 100 mV
Industrial
–40°C to +85°C 3.3V ± 165 mV 1.8V ± 100mV
Electrical Characteristics Over the Operating Range
Parameter
Description
Part No.
–167
–133
–100
Unit
Min.
Typ
Max
Min.
Typ
Max
Min.
Typ
Max
VOH
Output HIGH Voltage (VDD = Min., IOH =
–4.0 mA)
2.4
2.4
2.4
V
VOL
Output LOW Voltage (VDD = Min., IOL= +4.0
mA)
0.4
0.4
0.4
V
VIH
Input HIGH Voltage
2.0
2.0
2.0
V
VIL
Input LOW Voltage
0.8
0.8
0.8
V
IOZ
Output Leakage Current
–10
10
–10
10
–10
10
µA
IIX1
Input Leakage Current Except TDI, TMS,
MRST
–10
10
–10
10
–10
10
µA
IIX2
Input Leakage Current TDI, TMS, MRST
–0.1
1.0
–0.1
1.0
–0.1
1.0
mA
ICC
Operating Current
(VDD = Max.,IOUT = 0 mA),
Outputs Disabled
CYD04S72V
225
300
225
300
mA
CYD09S72V
406
580
350
500
CYD18S72V
410
580
315
450
mA
ISB1
Standby Current
(Both Ports TTL Level)
CEL and CER ≥ VIH, f = fMAX
CYD04S72V
90
115
90
115
mA
CYD09S72V
105
150
105
150
ISB2
Standby Current
(One Port TTL Level)
CEL | CER ≥ VIH, f = fMAX
CYD04S72V
160
210
160
210
mA
CYD09S72V
266
380
266
380
ISB3
Standby Current (Both
Ports CMOS Level) CEL
and CER ≥ VDD – 0.2V, f = 0
CYD04S72V
CYD09S72V
55
75
55
75
mA
ISB4
Standby Current
(One Port CMOS Level)
CEL | CER ≥ VIH, f = fMAX
CYD04S72V
160
210
160
210
mA
CYD09S72V
224
320
224
320
ISB5
Operating Current (VDDIO
= Max, Iout = 0 mA, f = 0)
Outputs Disabled
CYD18S72V
75
75
mA
ICORE[11]
Core Operating Current for (VDD = Max.,
IOUT = 0 mA), Outputs Disabled
00
00
0
0
mA
Notes:
22. The voltage on any input or I/O pin can not exceed the power pin during power-up.
23. Pulse width < 20 ns.
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