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CY62148BN MoBL®
Document #: 001-06517 Rev. *B
Page 4 of 9
Notes
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any
of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write.
Switching Characteristics[5] Over the Operating Range
Parameter
Description
CY62148BN
Unit
Min
Max
READ CYCLE
tRC
Read Cycle Time
70
ns
tAA
Address to Data Valid
70
ns
tOHA
Data Hold from Address Change
10
ns
tACE
CE LOW to Data Valid
70
ns
tDOE
OE LOW to Data Valid
35
ns
tLZOE
OE LOW to Low Z[6]
5
ns
tHZOE
OE HIGH to High Z[6, 7]
25
ns
tLZCE
CE LOW to Low Z[6]
10
ns
tHZCE
CE HIGH to High Z[6, 7]
25
ns
tPU
CE LOW to Power Up
0
ns
tPD
CE HIGH to Power Down
70
ns
WRITE CYCLE[8]
tWC
Write Cycle Time
70
ns
tSCE
CE LOW to Write End
60
ns
tAW
Address Setup to Write End
60
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Setup to Write Start
0
ns
tPWE
WE Pulse Width
55
ns
tSD
Data Setup to Write End
30
ns
tHD
Data Hold from Write End
0
ns
tLZWE
WE HIGH to Low Z[6]
5
ns
tHZWE
WE LOW to High Z[6, 7]
25
ns
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