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CY62138F Datasheet(PDF) 5 Page - Cypress Semiconductor

Part No. CY62138F
Description  2-Mbit (256K x 8) Static RAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY62138F Datasheet(HTML) 5 Page - Cypress Semiconductor

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Document #: 001-13194 Rev. *A
Page 5 of 10
CY62138F MoBL®
Switching Characteristics (Over the Operating Range) [11]
Parameter
Description
45 ns
Unit
Min
Max
Read Cycle
tRC
Read Cycle Time
45
ns
tAA
Address to Data Valid
45
ns
tOHA
Data Hold from Address Change
10
ns
tACE
CE1 LOW and CE2 HIGH to Data Valid
45
ns
tDOE
OE LOW to Data Valid
22
ns
tLZOE
OE LOW to Low-Z [12]
5ns
tHZOE
OE HIGH to High-Z [12, 13]
18
ns
tLZCE
CE1 LOW and CE2 HIGH to Low Z
[12]
10
ns
tHZCE
CE1 HIGH or CE2 LOW to High-Z
[12, 13]
18
ns
tPU
CE1 LOW and CE2 HIGH to power up
0
ns
tPD
CE1 HIGH or CE2 LOW to power down
45
ns
Write Cycle [14]
tWC
Write Cycle Time
45
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
35
ns
tAW
Address Setup to Write End
35
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Setup to Write Start
0
ns
tPWE
WE Pulse Width
35
ns
tSD
Data Setup to Write end
25
ns
tHD
Data Hold from Write End
0
ns
tHZWE
WE LOW to High-Z [12, 13]
18
ns
tLZWE
WE HIGH to Low-Z [12]
10
ns
Notes
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the AC Test Loads and Waveforms on page 4.
12. At any given temperature and voltage condition, tHZCE is less than tLZCE , tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
13. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.
14. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
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